Datasheet

USB 2.0 Hi-Speed Hub Controller
Datasheet
SMSC USB251xB/xBi 57 Revision 2.2 (02-17-12)
DATASHEET
7.2 External Clock
50% duty cycle ± 10%, 24 MHz ± 350 ppm, jitter < 100 ps rms.
The external clock is recommended to conform to the signaling level designated in the
JESD76-2
Specification
[5] on 1.2 V CMOS Logic. XTALOUT should be treated as a weak (<1mA) buffer output.
7.2.1 SMBus Interface
The SMSC hub conforms to all voltage, power, and timing characteristics and specifications as set
forth in the
SMBus 1.0 Specification [3] for slave-only devices (except as noted in Section 5.3: SMBus
on page 42.
7.2.2 I
2
C EEPROM
Clock frequency is fixed at 60 kHz ± 20%.
7.2.3 USB 2.0
The SMSC hub conforms to all voltage, power, and timing characteristics and specifications as set
forth in the
USB 2.0 Specification [1].