Datasheet
MCP6S21/2/6/8
DS21117B-page 16 2003-2012 Microchip Technology Inc.
4.0 ANALOG FUNCTIONS
The MCP6S21/2/6/8 family of Programmable Gain
Amplifiers (PGA) are based on simple analog building
blocks (see Figure 4-1). Each of these blocks will be
explained in more detail in the following sub-sections.
FIGURE 4-1: PGA Block Diagram.
4.1 Input MUX
The MCP6S21 has one input, the MCP6S22 and
MCP6S25 have two inputs, the MCP6S26 has six
inputs and the MCP6S28 has eight inputs (see
Figure 4-1).
For the lowest input current, float unused inputs. Tying
these pins to a voltage near the used channels also
works well. For simplicity, they can be tied to V
SS
or
V
DD
, but the input current may increase.
The one channel MCP6S21 has the lowest input bias
current, while the eight channel MCP6S28 has the
highest. There is about a 2:1 ratio in I
B
between these
parts.
4.2 Internal Op Amp
The internal op amp provides the right combination of
bandwidth, accuracy and flexibility.
4.2.1 COMPENSATION CAPACITORS
The internal op amp has three compensation capaci-
tors connected to a switching network. They are
selected to give good small signal bandwidth at high
gains, and good slew rate (full power bandwidth) at low
gains. The change in bandwidth as gain changes is
between 2 MHz and 12 MHz. Refer to Table 4-1 for
more information.
TABLE 4-1: GAIN VS. INTERNAL COMPENSATION CAPACITOR
MCP6S21–One input (CH0), no SO pin
MCP6S22–Two inputs (CH0, CH1), V
REF
tied internally
to V
SS
, no SO pin
MCP6S26–Six inputs (CH0 to CH5)
MCP6S28–Eight inputs (CH0 to CH7)
V
OUT
V
REF
V
DD
CS
SI
SO
SCK
CH1
CH0
CH3
CH2
CH5
CH4
CH7
CH6
V
SS
8
R
F
R
G
MUX
SPI™
Logic
POR
Gain
Switches
+
-
Resistor Ladder (R
LAD
)
Gain
(V/V)
Internal
Compensation
Capacitor
Typical GBWP
(MHz)
Typical SR
(V/µs)
Typical FPBW
(MHz)
Typical BW
(MHz)
1 Large 12 4.0 0.30 12
2 Large 12 4.0 0.30 6
4Medium 20 11 0.70 10
5Medium 20 11 0.70 7
8 Medium 20 11 0.70 2.4
10 Medium 20 11 0.70 2.0
16 Small 64 22 1.6 5
32 Small 64 22 1.6 2.0
Note 1: FPBW is the Full Power Bandwidth. These numbers are based on V
DD
= 5.0V.
2: No changes in DC performance (e.g., V
OS
) accompany a change in compensation capacitor.
3: BW is the closed-loop, small signal -3 dB bandwidth.