Datasheet

PIC32MX1XX/2XX
DS60001168F-page 320 © 2011-2014 Microchip Technology Inc.
Revision F (February 2014)
This revision includes the addition of the following
devices:
In addition, this revision includes the following major
changes as described in Ta bl e A - 5, as well as minor
updates to text and formatting, which were
incorporated throughout the document.
• PIC32MX170F256B • PIC32MX270F256B
• PIC32MX170F256D • PIC32MX270F256D
TABLE A-5: MAJOR SECTION UPDATES
Section Update Description
32-bit Microcontrollers (up to 256
KB Flash and 64 KB SRAM) with
Audio and Graphics Interfaces,
USB, and Advanced Analog
Added new devices to the family features (see Tabl e 1 and Tab le 2 ).
Updated pin diagrams to include new devices (see “Pin Diagrams”).
1.0 “Device Overview” Added Note 3 reference to the following pin names: V
BUS, VUSB3V3, VBUSON,
D+, D-, and USBID.
2.0 “Guidelines for Getting
Started with 32-bit MCUs”
Replaced Figure 2-1: Recommended Minimum Connection.
Updated Figure 2-2: MCLR Pin Connections.
Added 2.9 “S
OSC Design Recommendation”.
4.0 “Memory Organization” Added memory tables for devices with 64 KB RAM (see Tab le 4 -4 through
Table 4-5).
Changed the Virtual Addresses for all registers and updated the PWP bits in
the DEVCFG: Device Configuration Word Summary (see Ta bl e 4 -1 7).
Updated the ODCA, ODCB, and ODCC port registers (see Tabl e 4- 1 9,
Table 4-20, and Table 4-21).
The RTCTIME, RTCDATE, ALRMTIME, and ALRMDATE registers were
updated (see Table 4-25).
Added Data Ram Size value for 64 KB RAM devices (see Register 4-5).
Added Program Flash Size value for 256 KB Flash devices (see Register 4-5).
12.0 “Timer1” The Timer1 block diagram was updated to include the 16-bit data bus (see
Figure 12-1).
13.0 “Timer2/3, Timer4/5” The Timer2-Timer5 block diagram (16-bit) was updated to include the 16-bit
data bus (see Figure 13-1).
The Timer2/3, Timer4/5 block diagram (32-bit) was updated to include the 32-
bit data bus (see Figure 13-1).
19.0 “Parallel Master Port (PMP)” The CSF<1:0> bit value definitions for ‘00’ and ‘01’ were updated (see
Register 19-1).
Bit 14 in the Parallel Port Address register (PMADDR) was updated (see
Register 19-3).
20.0 “Real-Time Clock and
Calendar (RTCC)”
The following registers were updated:
• RTCTIME (see Register 20-3)
• RTCDATE (see Register 20-4)
• ALRMTIME (see Register 20-5)
• ALRMDATE (see Register 20-6)
26.0 “Special Features” Updated the PWP bits (see Register 26-1).