Datasheet

PIC32MX1XX/2XX
DS60001168F-page 226 © 2011-2014 Microchip Technology Inc.
REGISTER 26-1: DEVCFG0: DEVICE CONFIGURATION WORD 0
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
r-0 r-1 r-1 R/P r-1 r-1 r-1 R/P
— — —CP— — —BWP
23:16
r-1 r-1 r-1 r-1 r-1 R/P R/P R/P
— — — — —PWP<8:6>
(3)
15:8
R/P R/P R/P R/P R/P R/P r-1 r-1
PWP<5:0> — —
7:0
r-1 r-1 r-1 R/P R/P R/P R/P R/P
— — — ICESEL<1:0>
(2)
JTAGEN
(1)
DEBUG<1:0>
Legend: r = Reserved bit P = Programmable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 Reserved: Write ‘0’
bit 30-29 Reserved: Write ‘1’
bit 28 CP: Code-Protect bit
Prevents boot and program Flash memory from being read or modified by an external programming device.
1 = Protection is disabled
0 = Protection is enabled
bit 27-25 Reserved: Write ‘1’
bit 24 BWP: Boot Flash Write-Protect bit
Prevents boot Flash memory from being modified during code execution.
1 = Boot Flash is writable
0 = Boot Flash is not writable
bit 23-19 Reserved: Write ‘1’
Note 1: This bit sets the value for the JTAGEN bit in the CFGCON register.
2: The PGEC4/PGED4 pin pair is not available on all devices. Refer to the “Pin Diagrams” section for
availability.
3: The PWP<8:7> bits are only available on devices with 256 KB Flash.