Datasheet

dsPIC33FJXXXMCX06A/X08A/X10A
DS70594D-page 194  2009-2012 Microchip Technology Inc.
REGISTER 17-1: QEIxCON: QEIx CONTROL REGISTER
R/W-0 U-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
CNTERR
— QEISIDL INDEX UPDN QEIM<2:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SWPAB PCDOUT TQGATE TQCKPS<1:0> POSRES TQCS UPDN_SRC
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CNTERR: Count Error Status Flag bit
1 = Position count error has occurred
0 = No position count error has occurred
(CNTERR flag only applies when QEIM<2:0> = ‘110’ or ‘100’)
bit 14 Unimplemented: Read as ‘0’
bit 13 QEISIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12 INDEX: Index Pin State Status bit (read-only)
1 = Index pin is High
0 = Index pin is Low
bit 11 UPDN: Position Counter Direction Status bit
1 = Position counter direction is positive (+)
0 = Position counter direction is negative (-)
(Read-only bit when QEIM<2:0> = ‘1xx’. Read/write bit when QEIM<2:0> = 001.)
bit 10-8 QEIM<2:0>: Quadrature Encoder Interface Mode Select bits
111 = Quadrature Encoder Interface enabled (x4 mode) with Position Counter Reset by match (MAXCNT)
110 = Quadrature Encoder Interface enabled (x4 mode) with Index Pulse Reset of position counter
101 = Quadrature Encoder Interface enabled (x2 mode) with Position Counter Reset by match (MAXCNT)
100 = Quadrature Encoder Interface enabled (x2 mode) with Index Pulse Reset of position counter
011 = Unused (module disabled)
010 = Unused (module disabled)
001 = Starts 16-bit Timer
000 = Quadrature Encoder Interface/timer off
bit 7 SWPAB: Phase A and Phase B Input Swap Select bit
1 = Phase A and Phase B inputs swapped
0 = Phase A and Phase B inputs not swapped
bit 6 PCDOUT: Position Counter Direction State Output Enable bit
1 = Position counter direction status output enable (QEI logic controls state of I/O pin)
0 = Position counter direction status output disabled (normal I/O pin operation)
bit 5 TQGATE: Timer Gated Time Accumulation Enable bit
1 = Timer gated time accumulation enabled
0 = Timer gated time accumulation disabled
Note 1: When configured for QEI mode, the control bit is a ‘don’t care’.