Datasheet
2001-2012 Microchip Technology Inc. DS21490D-page 13
TCN75
Timing Diagrams (Continued)
1
1
Start
by
Master
Ack
by
TCN75
Address Byte
(d) Typical Pointer Set Followed by Immediate Read from Configuration Register
Ack
by
TCN75
Repeat
Start
by
Master
Pointer Byte
Ack
by
TCN75
Stop
Cond
by
Maste
r
No Ack
by
Master
Address Byte
0000000D0 D7 D6 D5 D4 D3 D2 D1 D0100 A21 A1 A01 A2 A1 A0
R/W
00
19199
19
R/W
Data Byte
1
1
Start
by
Master
Ack
by
TCN75
Address Byte
(f) T
OS
and T
HYST
Write
Ack
by
TCN75
Pointer Byte
Ack
by
TCN75
Stop
Cond
by
Master
Ack
by
TCN75
Most Significant Data Byte
000000D1 D0 D7 D6 D5 D4 D3 D2 D1 D0D6 D5 D4 D2D3 D1 D01 A2 A1 A0
R/W
00
19199
19
D7
Least Significant Data Byte
1
1
Start
by
Master
Ack
by
TCN75T
Address Byte
(e) Configuration Register Write
Ack
by
TCN75
Pointer Byte
Ack
by
TCN75
Stop
Cond
by
Master
Configuration Byte
000000D1 D0 000D4 D2D3 D1 D01 A2 A1 A0
R/W
00
19199