TC9400/9401/9402 Voltage-to-Frequency / Frequency-to-Voltage Converters Features: General Description: VOLTAGE-TO-FREQUENCY The TC9400/9401/9402 are low-cost Voltage-to-Frequency (V/F) converters, utilizing low-power CMOS technology. The converters accept a variable analog input signal and generate an output pulse train, whose frequency is linearly proportional to the input voltage. • Choice of Linearity: - TC9401: 0.01% - TC9400: 0.05% - TC9402: 0.
TC9400/9401/9402 Functional Block Diagram Integrator Capacitor Input Voltage Integrator Op Amp Threshold Detector One Shot RIN IIN Pulse Output ÷2 Reference Capacitor Pulse/2 Output TC9400 IREF Reference Voltage DS21483D-page 2 © 2007 Microchip Technology Inc.
TC9400/9401/9402 1.0 ELECTRICAL CHARACTERISTICS † Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings † VDD – VSS ................................
TC9400/9401/9402 TC940X ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: unless otherwise specified, VDD = +5V, VSS = -5V, VGND = 0V, VREF = -5V, RBIAS = 100 kΩ, Full Scale = 10 kHz. TA = +25°C, unless temperature range is specified (-40°C to +85°C for E device, 0°C to +70°C for C device).
TC9400/9401/9402 TC940X ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: unless otherwise specified, VDD = +5V, VSS = -5V, VGND = 0V, VREF = -5V, RBIAS = 100 kΩ, Full Scale = 10 kHz. TA = +25°C, unless temperature range is specified (-40°C to +85°C for E device, 0°C to +70°C for C device). Parameter Min Typ Max Min Typ Max Min Typ Max Units Test Conditions Positive Excursion 0.4 — VDD 0.4 — VDD 0.
TC9400/9401/9402 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Pin No. 1 IBIAS 2 ZERO ADJ Description This pin sets bias current in the TC9400. Connect to VSS through a 100 kΩ resistor. Low frequency adjustment input. Input current connection for the V/F converter. 3 IIN 4 VSS 5 VREF OUT 6 GND Analog ground. 7 VREF Voltage reference input, typically -5V.
TC9400/9401/9402 2.6 Pulse Freq Out 2.9 This output is an open-drain N-channel FET, which provides a pulse waveform whose frequency is proportional to the input voltage. This output requires a pullup resistor and interfaces directly with MOS, CMOS, and TTL logic (see Figure 2-1). 2.7 Output Common The sources of both the FREQ/2 OUT and the PULSE FREQ OUT are connected to this pin.
TC9400/9401/9402 3.0 DETAILED DESCRIPTION 3.1 Voltage-to-Frequency (V/F) Circuit Description The TC9400 V/F converter operates on the principal of charge balancing. The operation of the TC9400 is easily understood by referring to Figure 3-1. The input voltage (VIN) is converted to a current (IIN) by the input resistor. This current is then converted to a charge on the integrating capacitor and shows up as a linearly decreasing voltage at the output of the op amp.
TC9400/9401/9402 3.2 Voltage-to-Time Measurements The TC9400 output can be measured in the time domain as well as the frequency domain. Some microcomputers, for example, have extensive timing capability, but limited counter capability. Also, the response time of a time domain measurement is only the period between two output pulses, while the frequency measurement must accumulate pulses during the entire counter time-base period.
TC9400/9401/9402 4.0 4.1 VOLTAGE-TO-FREQUENCY (V/F) CONVERTER DESIGN INFORMATION Input/Output Relationships The output frequency (FOUT) is related to the analog input voltage (VIN) by the transfer equation: 4.2.3 CREF The exact value is not critical and may be used to trim the full scale frequency (see Section 6.1 “Input/Output Relationships”, Input/Output Relationships). Glass film or air trimmer capacitors are recommended because of their stability and low leakage.
TC9400/9401/9402 The circuit of Figure 4-2 will directly interface with CMOS logic operating at 12V to 15V. TTL or 5V CMOS logic can be accommodated by connecting the output pull-up resistors to the +5V supply. An optoisolator can also be used if an isolated output is required; also, see Figure 4-3. Trimming the reference voltage is not recommended for high accuracy applications unless an op amp is used as a buffer, because the TC9400 requires a lowimpedance reference (see Section 2.
TC9400/9401/9402 V+ = 8V to 15V (Fixed) R2 R1 0.9Ω Offset Adjust RIN 1 MΩ 8 0.01 µF 10 kΩ 0.01 11 µF 0.2 R1 10 VREF FOUT/2 12 5 820 pF 180 pF 3 IIN VIN 0V–10V FOUT TC9400 7 2 kΩ 10 kΩ 2 6 5V 8.2 kΩ Gain Adjust 14 V2 IIN 1 4 9 100 kΩ V+ FIGURE 4-3: DS21483D-page 12 R1 R2 10V 1 MΩ 10 kΩ 12V 1.
TC9400/9401/9402 5.0 FREQUENCY-TO-VOLTAGE (F/V) CIRCUIT DESCRIPTION When used as an F/V converter, the TC9400 generates an output voltage linearly proportional to the input frequency waveform. Each zero crossing at the threshold detector’s input causes a precise amount of charge (q = CREF x VREF) to be dispensed into the op amp’s summing junction. This charge, in turn, flows through the feedback resistor, generating voltage pulses at the output of the op amp.
TC9400/9401/9402 6.0 6.1 F/V CONVERTER DESIGN INFORMATION 6.2 Input/Output Relationships The output voltage is related to the input frequency (FIN) by the transfer equation: EQUATION 6-1: VOUT = [VREF CREF RINT] FIN The response time to a change in FIN is equal to (RINT CINT). The amount of ripple on VOUT is inversely proportional to CINT and the input frequency. CINT can be increased to lower the ripple. Values of 1 µF to 100 µF are perfectly acceptable for low frequencies.
TC9400/9401/9402 V+ = 10V to 15V 14 10 kΩ VDD 6 GND .01 µF 6.2V TC9400 10 kΩ VREFOUT 500 kΩ 2 Zero Adjust 100 kΩ V+ Offset Adjust 33 kΩ Frequency Input 47 pF IIN 3 Amp Out 12 1.0 kΩ 0.01 µF 11 DET IN914 1.0 MΩ 0.1 µF 5 IBIAS GND 6 1 MΩ .001 µF VOUT VREF VSS 7 4 1.0 kΩ 100 kΩ Note: FIGURE 6-2: 6.3 The output is referenced to Pin 6, which is at 6.2V (Vz). For frequency meter applications, a 1 mA meter with a series scaling resistor can be placed across Pins 6 and 12.
TC9400/9401/9402 +5V V+ 14 VDD TC9400A TC9401A TC9402A Frequency Input Level Shifter FIN 42 V+ Output Common 9 * Threshold Detect 11 * FOUT 8 3 ms Delay *Optional If Buffer is Needed Threshold Detector VREF OUT 5 CREF 56 pF 12 pF Offset Adjust IIN 3 +5V 2 kΩ 100 kΩ 2 Zero Adjust 2.2 kΩ IBIAS VSS 1 60 pF Amp Out 12 – Op Amp + 4 VREF RINT 1 MΩ + See Figure 7-1: * FOUT/2 10 CINT 1000 pF VOUT GND 6 7 10 kΩ VREF (Typically -5V) -5V FIGURE 6-4: 6.4 DC – 10 kHz Converter.
TC9400/9401/9402 7.0 F/V POWER-ON RESET In some cases, however, the TC9400 output must be zero at power-on without a frequency input. In such cases, a capacitor connected from Pin 11 to VDD will usually be sufficient to pulse the TC9400 and provide a Power-on Reset (see Figure 7-1 (a) and (b)). Where predictable power-on operation is critical, a more complicated circuit, such as Figure 7-1 (b), may be required.
TC9400/9401/9402 8.0 PACKAGE INFORMATION 8.1 Package Marking Information 14-Lead CERDIP Example: (Front View) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN TC9400EJD 0731256 Example: (Back View) Y2026 Example: (Front View) 14-Lead PDIP XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN TC9400 CPD ^^ e3 0731256 Example: (Back View) Y2026 14-Lead SOIC (.150”) XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Example: (Front View) TC9400 EOD ^^e3 0731256 Example: (Back View) Y2026 Legend: XX...
TC9400/9401/9402 14-Lead Ceramic Dual In-Line (JD) – .300" Body [CERDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N E1 NOTE 1 1 2 D E A2 A c L A1 b1 b E2 e Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 14 Pitch e Top to Seating Plane A – – Standoff § A1 .015 – – Ceramic Package Height A2 .140 – .175 Shoulder to Shoulder Width E .290 – .
TC9400/9401/9402 14-Lead Plastic Dual In-Line (PD) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 14 Pitch e Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .
TC9400/9401/9402 14-Lead Plastic Small Outline (OD) – Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 e h b A A2 c φ L A1 β L1 Units Dimension Limits Number of Pins α h MILLIMETERS MIN N NOM MAX 14 Pitch e Overall Height A – 1.27 BSC – Molded Package Thickness A2 1.25 – – Standoff § A1 0.10 – 0.
TC9400/9401/9402 NOTES: DS21483D-page 22 © 2007 Microchip Technology Inc.
TC9400/9401/9402 APPENDIX A: REVISION HISTORY Revision D (September 2007) The following is the list of modifications: 1. 2. 3. 4. Corrected Figure 6-1. Added History section. Updated package marking information and package outline drawings Added Product identification System section. Revision C (May 2006) Revision B (May 2002) Revision A (April 2002) • Original Release of this Document. © 2007 Microchip Technology Inc.
TC9400/9401/9402 NOTES: DS21483D-page 24 © 2007 Microchip Technology Inc.
TC9400/9401/9402 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Device Temperature Range Package Examples: a) b) Device Temperature Range Package TC9400: Voltage-to-Frequency Converter TC9401: Voltage-to-Frequency Converter TC9402: Voltage-to-Frequency Converter E C = -40°C to +85°C (Extended) = 0°C to +70°C (Commercial) JD PD OD OD713 = = = = Ceramic Dual-Inline (.
TC9400/9401/9402 NOTES: DS21483D-page 26 © 2007 Microchip Technology Inc.
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