
TC77
DS20092B-page 4 2002-2012 Microchip Technology Inc.
FIGURE 1-1: Timing Diagrams.
CS
SCK
1/f
CLK
SI/O
t
DO
LSb
t
DIS
HI-Z
Data Output Timing
MSb
t
CS-SI/O
t
HD
t
SU
SI/O
SCK
CS
HI-Z
SI/O
SCK
CS
HI-Z
t
HD
t
SU
HI-Z
t
CS-SCK
SI/O Data Input Set-up and Hold Timing (Data is clocked on the rising edge of SCK)