Datasheet
2001-2013 Microchip Technology Inc. DS20001467B-page 7
TC7660S
4.0 DETAILED DESCRIPTION
4.1 Theory of Operation
The TC7660S contains all the necessary circuitry to
implement a voltage inverter, with the exception of two
external capacitors, which may be inexpensive 10 µF
polarized electrolytic capacitors. Operation is best
understood by considering Figure 4-2, which shows an
idealized voltage inverter. Capacitor C
1
is charged to a
voltage V
+
for the half cycle when switches S
1
and S
3
are closed. (Note: Switches S
2
and S
4
are open during
this half cycle.) During the second half cycle of opera-
tion, switches S
2
and S
4
are closed, with S
1
and S
3
open, thereby shifting capacitor C
1
negatively by V
+
volts. Charge is then transferred from C
1
negatively by
V
+
volts. Charge is then transferred from C
1
to C
2
, such
that the voltage on C
2
is exactly V
+
assuming ideal
switches and no load on C
2
.
The four switches in Figure 4-2 are MOS power
switches; S
1
is a P-channel device, and S
2
, S
3
and S
4
are N-channel devices. The main difficulty with this
approach is that in integrating the switches, the sub-
strates of S
3
and S
4
must always remain reverse-
biased with respect to their sources, but not so much as
to degrade their ON resistances. In addition, at circuit
start-up, and under output short circuit conditions
(V
OUT
= V
+
), the output voltage must be sensed and
the substrate bias adjusted accordingly. Failure to
accomplish this will result in high power losses and
probable device latch-up.
This problem is eliminated in the TC7660S by a logic
network which senses the output voltage (V
OUT
)
together with the level translators, and switches the
substrates of S
3
and S
4
to the correct level to maintain
necessary reverse bias.
FIGURE 4-1: TC7660S Test Circuit.
The voltage regulator portion of the TC7660S is an
integral part of the anti-latch-up circuitry. Its inherent
voltage drop can, however, degrade operation at low
voltages.
FIGURE 4-2: Ideal Charge Pump Inverter.
To improve low-voltage operation, the “LV” pin should
be connected to GND, disabling the regulator. For
supply voltages greater than 3.5V, the LV terminal must
be left open to ensure latch-up-proof operation and
prevent device damage.
4.2 Theoretical Power Efficiency
Considerations
In theory, a capacitive charge pump can approach
100% efficiency if certain conditions are met:
(1) The drive circuitry consumes minimal power.
(2) The output switches have extremely low ON
resistance and virtually no offset.
(3) The impedances of the pump and reservoir
capacitors are negligible at the pump frequency.
The TC7660S approaches these conditions for nega-
tive voltage multiplication if large values of C
1
and C
2
are used. Energy is lost only in the transfer of charge
between capacitors if a change in voltage occurs. The
energy lost is defined by:
E = 1/2 C
1
(V
1
2
– V
2
2
)
V
1
and V
2
are the voltages on C
1
during the pump and
transfer cycles. If the impedances of C
1
and C
2
are rel-
atively high at the pump frequency (refer to Figure 4-2)
compared to the value of R
L
, there will be a substantial
difference in voltages V
1
and V
2
. Therefore, it is desir-
able not only to make C
2
as large as possible to
eliminate output voltage ripple, but also to employ a
correspondingly large value for C
1
in order to achieve
maximum efficiency of operation.
4.3 Dos and Don'ts
• Do not exceed maximum supply voltages.
• Do not connect the LV terminal to GND for supply
voltages greater than 3.5V.
• Do not short circuit the output to V
+
supply for
voltages above 5.5V for extended periods; how-
ever, transient conditions including start-up are
okay.
• When using polarized capacitors in the inverting
mode, the + terminal of C
1
must be connected to
pin 2 of the TC7660S and the + terminal of C
2
must be connected to GND.
1
2
3
4
8
7
6
5
TC7660S
+
V
+
(+5V)
V
OUT
C
1
10 µF
C
OSC
+
C
2
10 µF
I
L
R
L
I
S
V
+
Note: For large values of C
OSC
(>1000 pF), the
values of C
1
and C
2
should be increased to
100F.
V
+
GND
S
3
S
1
S
2
S
4
C
2
V
OUT
= -V
IN
C
1
+
+