Datasheet

 2001-2012 Microchip Technology Inc. DS21463C-page 5
TC7650
tion region, where the main amplifier takes over from
the null amplifier. The clock frequency sets the transi-
tion region.
3.3 Intermodulation
Previous chopper stabilized amplifiers have suffered
from intermodulation effects between the chopper fre-
quency and input signals. These arise because the
finite AC gain of the amplifier results in a small AC sig-
nal at the input. This is seen by the zeroing circuit as an
error signal, which is chopped and fed back, thus inject-
ing sum and difference frequencies, and causing dis-
turbances to the gain and phase versus frequency
characteristics near the chopping frequency. These
effects are substantially reduced in the TC7650 by
feeding the nulling circuit with a dynamic current corre-
sponding to the compensation capacitor current in such
a way as to cancel that portion of the input signal due
to a finite AC gain. The intermodulation and gain/phase
disturbances are held to very low values, and can gen-
erally be ignored.
FIGURE 3-1: TC7650 CONTAINS A NULLING AND MAIN AMPLIFIER. OFFSET CORRECTION
VOLTAGES ARE STORED ON TWO EXTERNAL CAPACITORS
.
FIGURE 3-2: NULLING CAPACITOR
CONNECTION
3.4 Nulling Capacitor Connection
The offset voltage correction capacitors are connected
to C
A
and C
B
. The common capacitor connection is
made to V
SS
(Pin 4) on the 8-pin packages and to
capacitor return (C
RETN
, Pin 8) on the 14-pin packages.
The common connection should be made through a
separate PC trace or wire to avoid voltage drops. The
capacitors outside foil, if possible, should be connected
to C
RETN
or V
SS
.
3.5 Clock Operation
The internal oscillator is set for a 200Hz nominal chop-
ping frequency on both the 8- and 14-pin DIPs. With the
14-pin DIP TC7650, the 200 Hz internal chopping fre-
quency is available at the internal clock output (Pin 12).
A 400Hz nominal signal will be present at the external
clock input pin (Pin 13) with INT/EXT
high or open. This
is the internal clock signal before a divide-by-two oper-
ation.
The 14-pin DIP device can be driven by an external
clock. The INT/EXT
input (Pin 14) has an internal pull-
up and may be left open for internal clock operation. If
an external clock is used, INT/EXT
must be tied to V
SS
(Pin 7) to disable the internal clock. The external clock
signal is applied to the external clock input (Pin 13).
The external clock amplitude should swing between
V
DD
and ground for power supplies up to ±6V and
between V
+
and V
+
-6V for higher supply voltages.
At low frequencies the external clock duty cycle is not
critical, since an internal divide-by-two gives the
desired 50% switching duty cycle. The offset storage
correction capacitors are charged only when the exter-
nal clock input is high. A 50% to 80% external clock
Null
Main
Amplifier
Null
Amplifier
Gain = A
M
B
A
B
A
+
C
B
C
A
TC7650
Null
-
+
V
-
V
+
Gain = A
N
, Offset = V
OSN
V
OUT Analog Input
-
V
DD
V
SS
6
4
8
1
3
2
7
C
A
C
B
+
V
DD
TC7650
10
1
8
2
5
4
11
C
A
C
B
+
7
V
SS
14-PIN PACKAGE 8-PIN PACKAGE
TC7650
-
-