Datasheet

© 2011 Microchip Technology Inc. DS21743B-page 5
TC72
FIGURE 1-1: Serial Port Timing Diagrams.
CE
1/f
CLK
t
CL
t
CH
D7
D0
HIGH Z
SDI
SPI READ DATA TRANSFER
CE
1/f
CLK
t
CC
A7 = 1
t
CL
t
CH
D7 D0
SDI
A0
A7
t
DC
t
CDH
A0
t
F
t
R
t
DC
t
CDH
t
R
t
F
SCK
t
CC
(CP = 0, data shifted on rising edge of SCK, data clocked on falling edge of SCK, A7 = 0)
(CP = 0, data shifted on rising edge of SCK, data clocked on falling edge of SCK, A7 = 1)
t
CDD
SDO
SCK
t
CCH
t
CWH
t
CDZ
HIGH Z
t
CWH
t
CCH
Note: The timing diagram is drawn with CP = 0. The TC72 also functions with CP = 1;
however, the edges of SCK are reversed as defined in Table 4-3 and Figure 4-2.
SPI WRITE DATA TRANSFER
MSb
LSb
MSb
LSb
MSb LSb MSb LSb