Datasheet
Table Of Contents
- 1.0 Electrical characteristics
- 2.0 Pin Descriptions
- 3.0 Detailed Description
- 4.0 Typical Applications
- 4.1 TC7129 as a Replacement Part
- 4.2 Powering the TC7129
- 4.3 Connecting to External Logic
- 4.4 Temperature Compensation
- 4.5 RC Oscillator
- 4.6 Measuring Techniques
- 4.7 Dual-Slope Conversion
- 4.8 Successive Integration
- 4.9 Digital Auto-Zeroing
- 4.10 Inside the TC7129
- 4.11 Integrator Section
- 4.12 Continuity Indicator
- 4.13 Common and Digital Ground
- 4.14 Low Battery
- 4.15 Sequence and Results Counter
- 4.16 Overrange and Underrange Outputs
- 4.17 LATCH/Hold
- 4.18 Display Driver
- 5.0 Packaging Information
- 6.0 Revision History
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TC7129
DS21459E-page 8 2002-2012 Microchip Technology Inc.
Figure 3-1: Standard Circuit.
3.3 Integrating Capacitor (C
INT
)
The charge stored in the integrating capacitor during
the integrate phase is directly proportional to the input
voltage. The primary selection criterion for C
INT
is to
choose a value that gives the highest voltage swing
while remaining within the high-linearity portion of the
integrator output range. An integrator swing of 2V is the
recommended value. The capacitor value can be
calculated using the following equation:
EQUATION 3-1:
Using the values derived above (assuming 60 Hz
operation), the equation becomes:
EQUATION 3-2:
The capacitor should have low dielectric absorption to
ensure good integration linearity. Polypropylene and
Tef lo n
®
capacitors are usually suitable. A good
measurement of the dielectric absorption is to connect
the reference capacitor across the inputs by
connecting:
Pin-to-Pin:
20 33 (C
REF
+ to IN HI)
30 32 (C
REF
– to IN LO)
A reading between 10,000 and 9998 is acceptable;
anything lower indicates unacceptably high dielectric
absorption.
3.4 Reference Capacitor (C
REF
)
The reference capacitor stores the reference voltage
during several phases of the measurement cycle. Low
leakage is the primary selection criterion for this com-
ponent. The value must be high enough to offset the
effect of stray capacitance at the capacitor terminals. A
value of at least 1 F is recommended.
1234567
8
9
1011
12
13141516171819
20
40
39
3837
36
3534
33
323130
29
28
27262524232221
9V
+
Low Battery Continuity
V+
5 pF
120
kHz
10 pF
0.1 µF
20
kΩ
0.1
µF
100 kΩ
C
INT
0.1 µF
V+
V
IN
– +
330 kΩ
Crystal
R
O
C
O2
C
RF
D
REF
R
REF
C
IF
R
IF
C
REF
+
1 µF
10 kΩ
R
BIAS
150 kΩ
R
INT
OSC1
OSC3
ANNUNC
V
DISP
DP
4
/OR
Display Drive Outputs
DP
3
/UR
LATCH/
HOLD
V–
V+
INT IN
INT OUT
CONTINUITY
COMMON
C
REF
+
C
REF
–
BUFF
IN LO
IN HI
REF HI
REF LO
DGND
RANGE
DP
2
DP
1
OSC2
TC7129
C
O1
C
INT
=
t
INT
x I
INT
V
SWING
Where t
INT
is the integration time.
C
INT
= = 0.1 A
16.7 msec x 13.3 A
2V