Datasheet

TC7109/A
DS21456D-page 14  2002-2012 Microchip Technology Inc.
FIGURE 3-8: TC7109A Handshake – Typical UART Interface Timing
FIGURE 3-9: TC7109A Handshake Triggered by Mode Input
=
Three-State High-Impedance
Integrator Output
Data Valid
Internal Clock
Internal Latch
Status Output
Mode Input
Internal Mode
Send Input (UART TBRE)
CE/LOAD Output (UART TBRL)
HBEN
High Byte Data
LBEN
Low Byte Data
= Don't Care
UART
Norm
Terminates
UART Mode
Zero Crossing Detected
Zero Crossing Occurs
Send
Sensed
Send
Sensed
Send
Sensed
Data Valid
Data Valid
Data Valid
Terminates
UART Mode
=
Three-State
High-Impedance
Internal Clock
Internal Latch
Status Output
Mode Input
Internal Mode
Send Input
CE/LOAD as Output
HBEN
High Byte Data
LBEN
Low Byte Data
= Don't Care
=
Three-State
with Pull-up
UART
Norm
Send
Sensed
Send
Sensed
Zero Crossing Detected
Zero Crossing Occurs
Status Output unchanged
in UART Mode
Latch Pulse inhibited in UART Mod
e
Positive Transiton causes
Entry into UART Mode
DE Phase III
Send
Sensed