Datasheet

TC7109/A
DS21456D-page 10  2002-2012 Microchip Technology Inc.
FIGURE 3-1: Conversion Timing (RUN/HOLD) Pin High
FIGURE 3-2: Digital Section
Internal Clock
Integrator Output
for Normal Input
Integrator
Saturates
Internal Latch
Integrator Output
for Over Range Input
No Zero Crossing
ZI
AZ
Zero Integrator
Phase forces
Integrator Output
to 0V
Zero Crossing
Occurs
Zero Crossing
Detected
INT
Phase II
Status Output
AZ
Phase I
DE
Phase III
AZ
Fixed
2048
Counts
2048
Counts
Min.
4096
Counts
Max
Number of Counts to Zero Crossing
Proportional to V
IN
After Zero Crossing, Analog section will
be in Auto-Zero Configuration
TEST
17
POL
3
OR
4
B
12
5
B
11
6
B
10
7
B
9
8
B
8
9
B
7
10
B
6
11
B
5
12
B
4
13
B
3
14
2262223242521
STATUS RUN/
HOLD
OSC
IN
OSC
OUT
OSC
SEL
BUFF
OSC
OUT
MODE
To
Analog
Section
COMP OUT
AZ
INT
DE (±)
ZI
Conversion
Control Logic
Oscillator and
Clock Circuitry
High Order
Byte Outputs
Low Order
Byte Outputs
Handshake
Logic
B
2
15
B
1
16
27
SEND
18
19
20
LBEN
HBEN
CE/LOAD
1
GND
14 Latches
12-Bit Counter
14 Three-State Outputs
Latch
Clock