Datasheet

TC1016
DS21666B-page 10 © 2005 Microchip Technology Inc.
4.1 Input Capacitor
Low input source impedance is necessary for the LDO
to operate properly. When operating from batteries, or
in applications with long lead length (> 10") between
the input source and the LDO, some input capacitance
is required. A minimum of 0.1 µF is recommended for
most applications and the capacitor should be placed
as close to the input of the LDO as is practical. Larger
input capacitors will help reduce the input impedance
and further reduce any high-frequency noise on the
input and output of the LDO.
4.2 Output Capacitor
A minimum output capacitance of 1 µF for the TC1016
is required for stability. The ESR requirements on the
output capacitor are between 0 and 2 ohms. The output
capacitor should be located as close to the LDO output
as is practical. Ceramic materials X7R and X5R have
low temperature coefficients and are well within the
acceptable ESR range required. A typical 1 µF X5R
0805 capacitor has an ESR of 50 milli-ohms. Larger
output capacitors can be used with the TC1016 to
improve dynamic behavior and input ripple rejection
performance.
Ceramic, aluminum electrolytic or tantalum capacitor
types can be used. Since many aluminum electrolytic
capacitors freeze at approximately –30°C, ceramic or
solid tantalums are recommended for applications
operating below –25°C. When operating from sources
other than batteries, supply noise rejection and tran-
sient response can be improved by increasing the
value of the input and output capacitors, and by
employing passive filtering techniques.
4.3 Turn-On Response
The turn on response is defined as two separate
response categories, Wake-up Time (t
WK
) and Settling
Time (t
S
).
The TC1016 has a fast t
WK
(10 µsec, typ.) when
released from shutdown. Figure 4-3 provides the
TC1016’s t
WK
. The t
WK
is defined as the time it takes
for the output to rise to 2% of the V
OUT
value after being
released from shutdown.
The total turn-on response is defined as the t
S
(see
Figure 4-3). The t
S
(inclusive with t
WK
) is defined as the
condition when the output is within 98% of its fully
enabled value (42 µsec, typ.) when released from shut-
down. The settling time of the output voltage is
dependent on load conditions and output capacitance
on V
OUT
(RC response).
Table 4-1 demonstrates the typical turn-on response
timing for different input voltage power-up frequencies:
V
OUT
= 2.8V, V
IN
= 5.0V, I
OUT
= 60 mA and C
OUT
= 1 µF.
TABLE 4-1: TYPICAL TURN-ON
RESPONSE TIMING
FIGURE 4-3: Wake-Up Time from Shutdown.
Frequency Typical (t
WK
) Typical (t
S
)
1000 Hz 5.3 µsec 14 µsec
500 Hz 5.9 µsec 16 µsec
100 Hz 9.8 µsec 32 µsec
50 Hz 14.5 µsec 52 µsec
10 Hz 17.2 µsec 77 µsec
V
IH
t
S
t
WK
V
OUT
98%
2%
V
IL
SHDN