Datasheet

8 Mbit LPC Flash

SST49LF080A

Data Sheet

Microchip Technology Company

CE#

The CE# pin, enables and disables the SST49LF080A, controlling read and write access of the device.

To enable the SST49LF080A, the CE# pin must be driven low one clock cycle prior to LFRAME# being

driven low. The device will enter standby mode when internal Write operations are completed and CE#

is high.

LFRAME#

The LFRAME# signifies the start of a (frame) bus cycle or the termination of an undesired cycle.

Asserting LFRAME# for two or more clock cycle and driving a valid START value on LAD[3:0] will initi-

ate device operation. The device will enter standby mode when internal operations are completed and

LFRAME# is high.

TBL#, WP#

The Top Boot Lock (TBL#) and Write Protect (WP#) pins are provided for hardware write protection of

device memory. The TBL# pin is used to Write-Protect 16 boot sectors (64 KByte) at the highest mem-

ory address range for the SST49LF080A. The WP# pin write protects the remaining sectors in the

flash memory.

An active low signal at the TBL# pin prevents Program and Erase operations of the top boot sectors.

When TBL# pin is held high, the write protection of the top boot sectors is disabled. The WP# pin

serves the same function for the remaining sectors of the device memory. The TBL# and WP# pins

write protection functions operate independently of one another.

Both TBL# and WP# pins must be set to their required protection states prior to starting a Program or

Erase operation. A logic level change occurring at the TBL# or WP# pin during a Program or Erase

operation could cause unpredictable results.