Datasheet

8 Mbit LPC Flash

SST49LF080A

Data Sheet

Microchip Technology Company

Design Considerations

SST recommends a high frequency 0.1 µF ceramic capacitor to be placed as close as possible

between V

and V

less than 1 cm away from the V

pin of the device. Additionally, a low fre-

quency 4.7 µF electrolytic capacitor from V

to V

should be placed within 5 cm of the V

pin. If you

use a socket for programming purposes add an additional 1-10 µF next to each socket.

Product Identification

The Product Identification mode identifies the device as the SST49LF080A and manufacturer as SST.

Mode Selection

The SST49LF080A flash memory devices can operate in two distinct interface modes: the LPC mode

and the Parallel Programming (PP) mode. The mode pin is used to set the interface mode selection. If

the mode pin is set to logic High, the device is in PP mode. If the mode pin is set Low, the device is in

the LPC mode. The mode selection pin must be configured prior to device operation. The mode pin is

internally pulled down if the pin is left unconnected. In LPC mode, the device is configured to its host

using standard LPC interface protocol. Communication between Host and the SST49LF080A occurs

via the 4-bit I/O communication signals, LAD [3:0] and LFRAME#. In PP mode, the device is pro-

grammed via an 11-bit address and an 8-bit data I/O parallel signals. The address inputs are multi-

plexed in row and column selected by control signal R/C# pin. The row addresses are mapped to the

lower internal addresses (A

10-0

), and the column addresses are mapped to the higher internal

addresses (A

MS-11

). See Figure 4, the Device Memory Map, for address assignments.

Table 2: Product Identification

Address Data

Manufacturer’s ID 0000H BFH

Device ID

SST49LF080A 0001H 5BH

T2.0 25026