Datasheet

©2011 Silicon Storage Technology, Inc. DS25086A 11/11
34
8 Mbit LPC Flash
SST49LF080A
Data Sheet
A
Microchip Technology Company
Figure 17:Reset Timing Diagram (PP Mode)
Table 25:Reset Timing Parameters, V
DD
=3.0-3.6V (PP Mode)
Symbol Parameter Min Max Units
T
PRST
V
DD
stable to Reset Low 1 ms
T
RSTP
RST# Pulse Width 100 ns
T
RSTF
RST# Low to Output Float 48 ns
T
RST
1
RST# High to Row Address Setup 1 µs
T
RSTE
RST# Low to reset during Sector-/Block-Erase or Pro-
gram
10 µs
T
RSTC
RST# Low to reset during Chip-Erase 50 µs
T25.0 25026
1. There may be additional reset latency due to T
RSTE
or T
RSTC
if a reset procedure is performed during a Program or
Erase operation.
V
DD
RST#
Addresses
R/C#
DQ
7-0
1235 F16.0
T
PRST
T
RSTP
T
RSTF
T
RSTE
Row Address
Sector-/Block-Erase
or Program operation
aborted
T
RST
T
RSTC
Chip-Erase
aborted