Datasheet

©2011 Silicon Storage Technology, Inc. DS25086A 11/11
30
8 Mbit LPC Flash
SST49LF080A
Data Sheet
A
Microchip Technology Company
Figure 14:Reset Timing Diagram (LPC Mode)
Table 19:Reset Timing Parameters, V
DD
=3.0-3.6V (LPC Mode)
Symbol Parameter Min Max Units
T
PRST
V
DD
stable to Reset Low 1 ms
T
KRST
Clock Stable to Reset Low 100 µs
T
RSTP
RST# Pulse Width 100 ns
T
RSTF
RST# Low to Output Float 48 ns
T
RST
1
RST# High to LFRAME# Low 1 µs
T
RSTE
RST# Low to reset during Sector-/Block-Erase or Pro-
gram
10 µs
T19.0 25026
1. There may be additional latency due toT
RSTE
if a reset procedure is performed during a Program or Erase operation.
CLK
V
DD
RST#/INIT#
LFRAME#
LAD[3:0]
1235 F13.0
T
PRST
T
KRST
T
RSTP
T
RSTF
T
RSTE
Sector-/Block-Erase
or Program operation
aborted
T
RST