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ManualsBrandsMICROCHIP TECHNOLOGY ManualsIntegrated Circuits (ICs)TSOP 32 8 Bit 1 M x 8
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©2011 Silicon Storage Technology, Inc. DS25086A 11/11
25
8 Mbit LPC Flash
SST49LF080A
Data Sheet
A
Microchip Technology Company
Figure 11:Block-Erase Command Sequence (LPC Mode)
1235 F10.0
LFRAME#
LAD[3:0]
0000b 011Xb A[23:20] A[19:16] 0101b 0101b 0101b 1010b0101b 1010b Tri-State
TA R
Load Address YYYY 5555H in 8 Clocks
Write the 1st command to the device in LPC mode.
Address
1
1 Clock 1 Clock
1st Start
Memory
Write
Cycle
TA R
SyncData
Start next
Command
1 Clock
1 Clock2 ClocksLoad Data AAH in 2 Clocks
1111b 0000b
LCLK
LFRAME#
LAD[3:0]
0000b 011Xb
A[23:20]
A[19:16] 1010b 1010b 1010b 0101b0010b 0101b Tri-State
TA R
Load Address YYYY 2AAAH in 8 Clocks
Write the 2nd command to the device in LPC mode.
Address
1
1 Clock 1 Clock
2nd Start
Memory
Write
Cycle
TA R
SyncData
Start next
Command
1 Clock
1 Clock2 ClocksLoad Data 55H in 2 Clocks
1111b 0000b
LCLK
LFRAME#
LAD[3:0]
0000b 011Xb A[23:20] A[19:16] 0101b 0101b 0101b 1000b0101b 0000b Tri-State
TA R
Load Address YYYY 5555H in 8 Clocks
Write the 3rd command to the device in LPC mode.
Address
1
1 Clock 1 Clock
3rd Start
Memory
Write
Cycle
TA R
SyncData
Start next
Command
1 Clock
1 Clock2 ClocksLoad Data 80H in 2 Clocks
1111b 0000b
LCLK
LFRAME#
LAD[3:0]
0000b 011Xb A[23:20] A[19:16] 0101b 0101b 0101b 1010b0101b 1010b Tri-State
TA R
Load Address YYYY 5555H in 8 Clocks
Write the 4th command to the device in LPC mode.
Address
1
1 Clock 1 Clock
4th Start
Memory
Write
Cycle
TA R
SyncData
Start next
Command
1 Clock
1 Clock2 ClocksLoad Data AAH in 2 Clocks
1111b 0000b
LCLK
LFRAME#
LAD[3:0]
0000b 011Xb
A[23:20] A[19:16] 1010b 1010b 1010b 0101b0010b 0101b
A[19:16] XXXXb XXXXb XXXXb 0101b
BA
X
0000b
Tri-State
TA R
Load Address YYYY 2AAAH in 8 Clocks
Load Block Address in 8 Clocks
Write the 5th command to the device in LPC mode.
Address
1
1 Clock 1 Clock
5th
Memory
Write
Cycle
TA R
SyncData
Start next
Command
1 Clock
1 Clock2 ClocksLoad Data 55H in 2 Clocks
Load Data “50” in 2 Clocks
1111b 0000b
LCLK
LFRAME#
LAD[3:0]
0000b 011Xb A[23:20] Tri-State
TA R
Write the 6th command (target sector to be erased) to the device in LPC mode.
BA
X
= Block Address
Address
1
1 Clock 1 Clock
6th Start
Memory
Write
Cycle
TA R
SyncData
Internal
erase start
Internal
erase start
1 Clock2 Clocks
1111b 0000b
CE#
CE#
CE#
CE#
CE#
LCLK
CE#
A[31:28] A[27:24]
A[31:28] A[27:24]
A[31:28] A[27:24]
A[31:28] A[27:24]
A[31:28] A[27:24]
A[31:28] A[27:24]
Note: 1. Address must be within memory address range specified in Table 4.