Datasheet

©2011 Silicon Storage Technology, Inc. DS25086A 11/11
23
8 Mbit LPC Flash
SST49LF080A
Data Sheet
A
Microchip Technology Company
Figure 9: Toggle Bit Command Sequence (LPC Mode)
1235 F08.0
LFRAME#
LAD[3:0]
0000b 011Xb A[11:8] A[7:4] A[3:0] D[7:4] A[15:12] D[3:0] Tri-State
TA R
Load Address in 8 Clocks
Write the last command (Program or Erase) to the device in LPC mode.
Address
1
1 Clock 1 Clock
1st Start
Memory
Write
Cycle
TA R
SyncData
Start next
Command
1 Clock
1 Clock2 ClocksLoad Data in 2 Clocks
1111b 0000b
0000b
LCLK
LFRAME#
LAD[3:0]
0000b 010Xb X,D6#,XXb XXXXbTri-State
TA R
Load Address in 8 Clocks
Read the DQ
6
to see if internal write complete or not.
Address
1
1 Clock 1 Clock
Start
Memory
Read
Cycle
TA R
Sync Data
Next start
1 Clock
Data out 2 Clocks1 Clock2 Clocks
1111b 0000b
0000b
LCLK
LFRAME#
LAD[3:0]
0000b 010Xb X,D6,XXb XXXXbTri-State
TA R
Load Address in 8 Clocks
When internal write complete, the DQ
6
will stop toggle.
Address
1
1 Clock 1 Clock
Start
Memory
Read
Cycle
TA R
Sync Data
Next start
1 Clock
Data out 2 Clocks1 Clock2 Clocks
1111b 0000b
0000b
CE#
CE#
LCLK
CE#
A[11:8] A[7:4] A[3:0] A[15:12]
A[11:8] A[7:4] A[3:0] A[15:12]
A[23:20] A[19:16]
A[23:20] A[19:16]
A[23:20] A[19:16]
A[31:28] A[27:24]
A[31:28] A[27:24]
A[31:28] A[27:24]
Note: 1. Address must be within memory address range specified in Table 4.