Datasheet

©2011 Silicon Storage Technology, Inc. DS25086A 11/11
14
8 Mbit LPC Flash
SST49LF080A
Data Sheet
A
Microchip Technology Company
Toggle Bit
During the internal Program or Erase operation, any consecutive attempts to read D[6] will produce
alternating 0s and 1s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is
completed, the toggling will stop.
Multiple Device Selection
Multiple LPC flash devices may be strapped to increase memory densities in a system. The four ID
pins, ID[3:0], allow up to 16 devices to be attached to the same bus by using different ID strapping in a
system. BIOS support, bus loading, or the attaching bridge may limit this number. The boot device
must have an ID of 0 (determined by ID[3:0]); subsequent devices use incremental numbering. Equal
density must be used with multiple devices.
When used as a boot device, ID[3:0] must be strapped as 0000; all subsequent devices should use a
sequential up-count strapping (i.e. 0001, 0010, 0011, etc.). With the hardware strapping, ID informa-
tion is included in every LPC address memory cycle. The ID bits in the address field are inverse of the
hardware strapping. The address bits [A
24
:A
23
,A
21
:A
20
] are used to select the device with proper IDs.
See Table 7 for IDs. The SST49LF080A will compare these bits with ID[3:0]’s strapping values. If there
is a mismatch, the device will ignore the remainder of the cycle.
Table 7: Multiple Device Selection Configuration
Device #
Hardware Strapping Address Bits Decoding
ID[3:0] A
24
A
23
A
21
A
20
0 (Boot device) 0000 1 1 1 1
1 0001 1 1 1 0
2 0010 1 1 0 1
3 0011 1 1 0 0
4 0100 1 0 1 1
5 0101 1 0 1 0
6 0110 1 0 0 1
7 0111 1 0 0 0
8 1000 0 1 1 1
9 1001 0 1 1 0
10 1010 0 1 0 1
11 1011 0 1 0 0
12 1100 0 0 1 1
13 1101 0 0 1 0
14 1110 0 0 0 1
15 1111 0 0 0 0
T7.0 25026