Datasheet

8 Mbit LPC Flash

SST49LF080A

Data Sheet

Microchip Technology Company

Response To Invalid Fields

During LPC Read/Write operations, the SST49LF080A will not explicitly indicate that it has received

invalid field sequences. The response to specific invalid fields or sequences is as follows:

Address out of range: The SST49LF080A will only respond to address ranges as specified in Table 4.

ID mismatch: ID information is included in every address cycle. The SST49LF080A will compare ID

bits in the address field with the hardware ID strapping. If there is a mis-match, the device will ignore

the cycle. See Multiple Device Selection section for details.

Once valid START, CYCTYPE + DIR, valid address range and ID bits are received, the SST49LF080A

will always complete the bus cycle. However, if the device is busy performing a flash Erase or Program

operation, no new internal Write command (memory write or register write) will be executed. As long

as the states of LAD[3:0] and LAD[4] are known, the response of the SST49LF080A to signals

received during the LPC cycle should be predictable.

Abort Mechanism

If LFRAME# is driven low for one or more clock cycles after the start of an LPC cycle, the cycle will be

terminated. The host may drive the LAD[3:0] with ‘1111b’ (ABORT nibble) to return the interface to

ready mode. The ABORT only affects the current bus cycle. For a multi-cycle command sequence,

such as the Erase or Program SDP commands, ABORT doesn’t interrupt the entire command

sequence, but only the current bus cycle of the command sequence. The host can re-send the bus

cycle and continue the SDP command sequence after the device is ready again.

Write Operation Status Detection

The SST49LF080A device provides two software means to detect the completion of a Write (Program

or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two

status bits: Data# Polling, D[7], and Toggle Bit, D[6]. The End-of-Write detection mode is incorporated

into the LPC Read Cycle. The actual completion of the nonvolatile write is asynchronous with the sys-

tem; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of

the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may

appear to conflict with either D[7] or D[6]. In order to prevent spurious rejection, if an erroneous result

occurs, the software routine should include a loop to read the accessed location an additional two (2)

times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is

valid.

Data# Polling

When the SST49LF080A device is in the internal Program operation, any attempt to read D[7] will pro-

duce the complement of the true data. Once the Program operation is completed, D[7] will produce

true data. Note that even though D[7] may have valid data immediately following the completion of an

internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data

bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase

operation, any attempt to read D[7] will produce a ‘0’. Once the internal Erase operation is completed,

D[7] will produce a ‘1’. Proper status will not be given using Data# Polling if the address is in the invalid

range.