Datasheet

©2011 Silicon Storage Technology, Inc. DS25086A 11/11
12
8 Mbit LPC Flash
SST49LF080A
Data Sheet
A
Microchip Technology Company
Figure 6: LPC Write Cycle Waveform
Table 6: LPC Write Cycle
Clock
Cycle
Field
Name
Field
Contents
LAD[3:0]
1
LAD[3:0]
Direction Comments
1 START 0000 IN LFRAME# must be active (low) for the part to
respond. Only the last start field (before
LFRAME# transitions high) should be recog-
nized.
2 CYCTYPE
+ DIR
011X IN Indicates the type of cycle. Bits 3:2 must be
“01b” for memory cycle. Bit 1 indicates the
type of transfer “1” for Write. Bit 0 is reserved.
3-10 ADDRESS YYYY IN Address Phase for Memory Cycle. LPC protocol
supports a 32-bit address phase. YYYY is one
nibble of the entire address. Addresses are
transferred most-significant nibble first. See
Table 3 for address bits definition and Table 4 for
valid memory address range.
11 DATA ZZZZ IN This field is the least-significant nibble of the data
byte.
12 DATA ZZZZ IN This field is the most-significant nibble of the
data byte.
13 TAR0 1111 IN then Float In this clock cycle, the host has driven the bus to
all ‘1’s and then floats the bus. This is the first
part of the bus “turnaround cycle.”
14 TAR1 1111 (float) Float then
OUT
The SST49LF080A takes control of the bus dur-
ing this cycle.
15 SYNC 0000 OUT The SST49LF080A outputs the values 0000, indicat-
ing that it has received data or a flash command.
16 TAR0 1111 OUT then
Float
In this clock cycle, the SST49LF080A has driven
the bus to all ‘1’s and then floats the bus. This is
the first part of the bus “turnaround cycle.”
17 TAR1 1111 (float) Float then IN Host resumes control of the bus during this cycle.
T6.0 25026
1. Field contents are valid on the rising edge of the present clock cycle.
1235 F05.0
LFRAME#
LAD[3:0]
0000b 011Xb A[23:20] A[19:16] A[3:0]A[7:4]A[11:8]A[15:12] 1111b Tri-State
2Clocks
TA R 0
Load Address in 8 Clocks
Address
1Clock 1Clock
Start
CYCTYPE
+
DIR
TA R
1Clock
Sync
Data
Load Data in 2 Clocks
0000bD[7:4]D[3:0]
LCLK
CE#
A[31:28] A[27:24]
Data TA R 1