8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet The SST49LF080A flash memory device is designed to interface with the LPC bus for PC and Internet Appliance application in compliance with Intel Low Pin Count (LPC) Interface Specification 1.0. Two interface modes are supported: LPC mode for in-system operations and Parallel Programming (PP) mode to interface with programming equipment.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Product Description The SST49LF080A flash memory device is designed to interface with the LPC bus for PC and Internet Appliance application in compliance with Intel Low Pin Count (LPC) Interface Specification 1.0. Two interface modes are supported: LPC mode for in-system operations and Parallel Programming (PP) mode to interface with programming equipment.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Functional Block Diagram TBL# WP# INIT# X-Decoder SuperFlash Memory LAD[3:0] LCLK LFRAME# LPC Interface Address Buffers Latches Y-Decoder ID[3:0] GPI[4:0] R/C# A[10:0] DQ[7:0] Control Logic I/O Buffers and Data Latches Programmer Interface OE# WE# MODE RST# CE# 1235 B1.0 Figure 1: Functional Block Diagram ©2011 Silicon Storage Technology, Inc.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet NC 2 1 A10 (GPI4) RST# (RST#) 3 R/C# (LCLK) A9 (GPI3) 4 VDD (VDD) A8 (GPI2) Pin Assignments 32 31 30 29 A7(GPI1) 5 A6 (GPI0) 6 28 NC (CE#) A5 (WP#) 7 27 NC A4 (TBL#) 8 26 NC A3 (ID3) 9 25 VDD (VDD) A2 (ID2) 10 24 OE# (INIT#) A1 (ID1) 11 23 WE# (LFRAME#) A0 (ID0) 12 22 NC DQ0 (LAD0) 13 21 14 15 16 17 18 19 20 DQ7 (RES) DQ6 (RES) DQ5 (RES) DQ4 (RES) DQ3 (LAD3) VSS (VSS) DQ2 (LAD2) DQ1
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Table 1: Pin Description Symbol A10-A0 Pin Name Address DQ7-DQ0 Data Type1 I I/O OE# WE# MODE Output Enable Write Enable Interface Mode Select I I I INIT# Initialize I ID[3:0] Identification Inputs I GPI[4:0] General Purpose Inputs I TBL# Top Block Lock I LAD[3:0] Address and Data LCLK Clock LFRAME# Frame I/O I I RST# WP# Reset Write Protect I I R/C# I RES VDD VSS CE# Row/Column Select Reserved Power Supply
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Device Memory Maps Block 15 TBL# Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 WP# for Block 0 14 0FFFFFH Boot Block 0F0000H 0EFFFFH 0E0000H 0DFFFFH 0D0000H 0CFFFFH 0C0000H 0BFFFFH 0B0000H 0AFFFFH 0A0000H 09FFFFH 090000H 08FFFFH 080000H 07FFFFH Block 7 Block 6 070000H 06FFFFH 060000H 05FFFFH Block 5 Block 4 050000H 04FFFFH 040000H 03FFFFH Block 3 Block 2 Block 1 Block 0 (64 KByte) 030000H 02FFFFH 020000H 01
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Design Considerations SST recommends a high frequency 0.1 µF ceramic capacitor to be placed as close as possible between VDD and VSS less than 1 cm away from the VDD pin of the device. Additionally, a low frequency 4.7 µF electrolytic capacitor from VDD to VSS should be placed within 5 cm of the VDD pin. If you use a socket for programming purposes add an additional 1-10 µF next to each socket.
Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet LPC Mode Device Operation The LPC mode uses a 5-signal communication interface, a 4-bit address/data bus, LAD[3:0], and a control line, LFRAME#, to control operations of the SST49LF080A. Cycle type operations such as Memory Read and Memory Write are defined in Intel Low Pin Count Interface Specification, Revision 1.0.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet CE# The CE# pin, enables and disables the SST49LF080A, controlling read and write access of the device. To enable the SST49LF080A, the CE# pin must be driven low one clock cycle prior to LFRAME# being driven low. The device will enter standby mode when internal Write operations are completed and CE# is high. LFRAME# The LFRAME# signifies the start of a (frame) bus cycle or the termination of an undesired cycle.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet INIT#, RST# A VIL on INIT# or RST# pin initiates a device reset. INIT# and RST# pins have the same function internally. It is required to drive INIT# or RST# pins low during a system reset to ensure proper CPU initialization. During a Read operation, driving INIT# or RST# pins low deselects the device and places the output drivers, LAD[3:0], in a high-impedance state.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Table 5: LPC Read Cycle Clock Cycle Field Name Field Contents LAD[3:0]1 LAD[3:0] Direction 1 START 0000 IN LFRAME# must be active (low) for the part to respond. Only the last start field (before LFRAME# transitions high) should be recognized. 2 CYCTYPE + DIR 010X IN Indicates the type of cycle. Bits 3:2 must be “01b” for memory cycle. Bit 1 indicates the type of transfer “0” for Read. Bit 0 is reserved.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Table 6: LPC Write Cycle Clock Cycle Field Name Field Contents LAD[3:0]1 LAD[3:0] Direction 1 START 0000 IN LFRAME# must be active (low) for the part to respond. Only the last start field (before LFRAME# transitions high) should be recognized. 2 CYCTYPE + DIR 011X IN Indicates the type of cycle. Bits 3:2 must be “01b” for memory cycle. Bit 1 indicates the type of transfer “1” for Write. Bit 0 is reserved.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Response To Invalid Fields During LPC Read/Write operations, the SST49LF080A will not explicitly indicate that it has received invalid field sequences. The response to specific invalid fields or sequences is as follows: Address out of range: The SST49LF080A will only respond to address ranges as specified in Table 4. ID mismatch: ID information is included in every address cycle.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Toggle Bit During the internal Program or Erase operation, any consecutive attempts to read D[6] will produce alternating 0s and 1s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. Multiple Device Selection Multiple LPC flash devices may be strapped to increase memory densities in a system.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Registers There are two registers available on the SST49LF080A, the General Purpose Inputs Registers (GPI_REG) and the JEDEC ID Registers. Since multiple LPC memory devices may be used to increase memory densities, these registers appear at its respective address location in the 4 GByte system memory map. Unused register locations will read as 00H.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet General Purpose Inputs Register The GPI_REG (General Purpose Inputs Register) passes the state of GPI[4:0] pins at power-up on the SST49LF080A. It is recommended that the GPI[4:0] pins be in the desired state before LFRAME# is brought low for the beginning of the next bus cycle, and remain in that state until the end of the cycle. There is no default value since this is a pass-through register.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Parallel Programming Mode Device Operation Commands are used to initiate the memory operation functions of the device. The data portion of the software command sequence is latched on the rising edge of WE#. During the software command sequence the row address is latched on the falling edge of R/C# and the column address is latched on the rising edge of R/C#.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Chip-Erase Operation The SST49LF080A devices provide a Chip-Erase operation, which allows the user to erase the entire memory array to the “1s” state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a six- byte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating ‘0’s and ‘1’s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# pulse for Program operation.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Software Command Sequence Table 11:Software Command Sequence 1st1 Cycle 2nd1 Cycle 3rd1 Cycle 4th1 Cycle 5th1 Cycle Command Sequence Addr2 Data Addr2 Data Addr2 Data Addr2 Data Byte-Program YYYY 5555H AAH YYYY 2AAA H 55H YYYY 5555 H A0H PA3 Data Sector-Erase YYYY 5555H AAH YYYY 2AAA H 55H YYYY 5555 H 80H YYYY 5555 H Block-Erase YYYY 5555H AAH YYYY 2AAA H 55H YYYY 5555 H 80H Chip-Erase6 YYYY 5555H
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet CE# LCLK LFRAME# LAD[3:0] 1st Start Memory Write Cycle 0000b 011Xb Address1 A[31:28] A[27:24] A[23:20] A[19:16] 1 Clock 1 Clock 0101b Data 0101b 0101b 0101b Load Address YYYY 5555H in 8 Clocks 1010b TAR 1010b 1111b Start next Command Sync TAR Tri-State 0000b Load Data AAH in 2 Clocks 2 Clocks 1 Clock 1 Clock Write the 1st command to the device in LPC mode.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet CE# LCLK LFRAME# 1st Start LAD[3:0] Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Address1 A[31:28] A[27:24] A[23:20] A[19:16] Data A[15:12] A[11:8] A[7:4] A[3:0] D[3:0] Dn[7:4] TAR Sync 1111b Tri-State 0000b 2 Clocks 1 Clock Load Data in 2 Clocks Load Address in 8 Clocks Start next Command 0000b TAR 1 Clock Write the last command (Program or Erase) to the device in LPC mode.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet CE# LCLK LFRAME# LAD[3:0] 1st Start Memory Write Cycle 0000b 011Xb 1 Clock 1 Clock Address1 Data A[19:16] A[15:12] A[11:8] A[31:28] A[27:24] A[23:20] A[7:4] Load Address in 8 Clocks A[3:0] D[3:0] TAR D[7:4] Load Data in 2 Clocks 1111b Start next Command 0000b Sync Tri-State 0000b 2 Clocks TAR 1 Clock 1 Clock Write the last command (Program or Erase) to the device in LPC mode.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet CE# LCLK LFRAME# Memory Write Cycle 1st Start LAD[3:0] 0000b 011Xb 1 Clock 1 Clock Address1 Data A[31:28] A[27:24] A[23:20] A[19:16] 0101b 0101b 0101b Load Address YYYY 5555H in 8 Clocks 0101b 1010b TAR 1010b 1111b Start next Command Sync Tri-State 0000b Load Data AAH in 2 Clocks 2 Clocks TAR 1 Clock 1 Clock Write the 1st command to the device in LPC mode.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet CE# LCLK LFRAME# 1st Start LAD[3:0] Memory Write Cycle Address1 011Xb A[31:28] A[27:24] A[23:20] A[19:16] 0000b Start next Command Data 0101b 0101b 0101b 0101b 1010b Sync TAR 1111b 1010b Tri-State 0000b Load Data AAH in 2 Clocks 2 Clocks Load Address YYYY 5555H in 8 Clocks Write the 1st command to the device in LPC mode.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet CE# LCLK LFRAME# Start LAD[3:0] 0000b Memory Read Cycle 010Xb Address1 A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] 1 Clock 1 Clock Load Address in 8 Clocks TAR A[7:4] A[3:0] 1111b Tri-State 2 Clocks Sync 0000b 1 Clock Start next Data D[3:0] D[7:4] 0000b TAR 1 Clock Data out 2 Clocks 1235 F11.0 Note: 1. See Table 9 for register addresses.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Electrical Specifications The AC and DC specifications for the LPC interface signals (LA0[3:0], LFRAME, LCLCK and RST#) as defined in Section 4.2.2.4 of the PCI local Bus specification, Rev. 2.1. Refer to Table 14 for the DC voltage and current specifications. Refer to Tables 18 through 21 and Tables 23 through 25 for the AC timing specifications for Clock, Read, Write, and Reset operations.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet DC Characteristics Table 14:DC Operating Characteristics (All Interfaces) Limits Symbol Parameter IDD1 Min Max Units Test Conditions Active VDD Current ISB LCLK (LPC mode) and Address Input (PP mode)=VILT/VIHT at f=33 MHz (LPC mode) or 1/TRC min (PP Mode) All other inputs=VIL or VIH Read 12 mA All outputs = open, VDD=VDD Max Write 24 mA See Note2 100 µA LCLK (LPC mode) and Address Input (PP mode)=VILT/VIHT Standby VD
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Table 16:Pin Capacitance (VDD=3.3V, Ta=25 °C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum CI/O1 I/O Pin Capacitance VI/O=0V 12 pF Input Capacitance VIN=0V 12 pF 1 CIN T16.0 25026 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Table 19:Reset Timing Parameters, VDD=3.0-3.6V (LPC Mode) Symbol Parameter TPRST VDD stable to Reset Low Min TKRST TRSTP TRSTF RST# Low to Output Float TRST1 RST# High to LFRAME# Low TRSTE RST# Low to reset during Sector-/Block-Erase or Program Max Units 1 ms Clock Stable to Reset Low 100 µs RST# Pulse Width 100 ns 48 ns 1 µs 10 µs T19.0 25026 1.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet AC Characteristics Table 20:Read/Write Cycle Timing Parameters, VDD=3.0-3.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet VTH LCLK VTEST VTL TVAL LAD [3:0] (Valid Output Data) LAD [3:0] (Float Output Data) TON TOFF 1235 F14.0 Figure 15:Output Timing Parameters (LPC Mode) VTH VTEST LCLK VTL TSU TDH LAD [3:0] (Valid Input Data) Inputs Valid VMAX 1235 F15.0 Figure 16:Input Timing Parameters (LPC Mode) Table 22:Interface Measurement Condition Parameters (LPC Mode) Symbol Value Units VTH1 0.6 VDD V 1 0.2 VDD V VTEST 0.4 VDD V 1 0.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Table 23:Read Cycle Timing Parameters, VDD=3.0-3.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Table 25:Reset Timing Parameters, VDD=3.0-3.6V (PP Mode) Symbol Parameter TPRST VDD stable to Reset Low TRSTP RST# Pulse Width TRSTF RST# Low to Output Float TRST 1 Min Max Units 1 ms 100 ns 48 RST# High to Row Address Setup ns 1 µs TRSTE RST# Low to reset during Sector-/Block-Erase or Program 10 TRSTC RST# Low to reset during Chip-Erase 50 µs µs T25.0 25026 1.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet RST# TRST TRC Addresses Row Address Column Address TAS TAS TAH Row Address Column Address TAH R/C# WE# VIH TAA OE# TOH TOE TOHZ TOLZ DQ7-0 High-Z Data Valid High-Z 1235 F17.0 Figure 18:Read Cycle Timing Diagram (PP Mode) TRST RST# Addresses Row Address TAS Column Address TAH TAS TAH R/C# TOEH TCWH OE# TOES TWPH TWP WE# TDS DQ7-0 TDH Data Valid 1235 F18.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Row Addresses Column R/C# WE# OE# TOEP D DQ7 D# D# D 1235 F19.0 Figure 20:Data# Polling Timing Diagram (PP Mode) Addresses Row Column R/C# WE# OE# TOET DQ6 D D 1235 F20.0 Figure 21:Toggle Bit Timing Diagram (PP Mode) A14-0 (Internal AMS-0) 5555 2AAA 5555 BA R/C# OE# WE# DQ7-0 Internal Program Starts 55 AA BA = Byte-Program Address AMS = Most Significant Address A0 DATA 1235 F21.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet A14-0 (Internal AMS-0) 5555 2AAA 5555 5555 2AAA SAX R/C# OE# WE# Internal Erase Starts DQ7-0 55 AA 80 AA 55 30 1235 F22.0 SAX = Sector Address Figure 23:Sector-Erase Timing Diagram (PP Mode) A14-0 (Internal AMS-0) 5555 2AAA 5555 5555 2AAA BAX R/C# OE# WE# Internal Erase Starts DQ7-0 55 AA 80 AA 55 50 1235 F23.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet A14-0 (Internal AMS-0) 2AAA 5555 5555 0000 0001 R/C# OE# TWP WE# TIDA TWPH DQ7-0 55 AA TAA BF 90 Device ID 1235 F25.0 Note: Device ID = 5BH for SST49LF080A Figure 26:Software ID Entry and Read (PP Mode) A14-0 (Internal AMS-0) 2AAA 5555 5555 R/C# OE# TIDA WE# DQ7-0 AA 55 F0 1235 F26.0 Figure 27:Software ID Exit (PP Mode) ©2011 Silicon Storage Technology, Inc.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1235 F27.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <3 ns.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Address: 5555H Write Data: AAH Cycle: 1 Address: 2AAAH Write Data: 55H Cycle: 2 Address: 5555H Write Data: A0H Cycle: 3 Address: AIN Write Data: DIN Cycle: 4 Wait TBP Available for Next Byte 1235 F30.0 Figure 31:Byte-Program Flowchart (LPC Mode) ©2011 Silicon Storage Technology, Inc.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Block-Erase Command Sequence Sector-Erase Command Sequence Address: 5555H Write Data: AAH Cycle: 1 Address: 5555H Write Data: AAH Cycle: 1 Address: 2AAAH Write Data: 55H Cycle: 2 Address: 2AAAH Write Data: 55H Cycle: 2 Address: 5555H Write Data: 80H Cycle: 3 Address: 5555H Write Data: 80H Cycle: 3 Address: 5555H Write Data: AAH Cycle: 4 Address: 5555H Write Data: AAH Cycle: 4 Address: 2AAAH Write Data: 55H Cycle: 5 Address:
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Software Product ID Entry Command Sequence Software Product ID Exit Command Sequence Address: 5555H Write Data: AAH Cycle: 1 Address: 5555H Write Data: AAH Cycle: 1 Address: XXXXH Write Data: F0H Cycle: 1 Address: 2AAAH Write Data: 55H Cycle: 2 Address: 2AAAH Write Data: 55H Cycle: 2 Wait TIDA Address: 5555H Write Data: 90H Cycle: 3 Address: 5555H Write Data: F0H Cycle: 3 Available for Next Command Wait TIDA Wait TIDA Add
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Start Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 1235 F33.0 Figure 34:Byte-Program Command Sequences Flowchart (PP Mode) ©2011 Silicon Storage Technology, Inc.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Internal Timer Toggle Bit Data# Polling ByteProgram/Erase Initiated ByteProgram/Erase Initiated ByteProgram/Erase Initiated Wait TBP, TSCE, TBE, or TSE Read byte Read DQ7 Read same byte Program/Erase Completed No Is DQ7 = true data Yes No Does DQ6 match Program/Erase Completed Yes Program/Erase Completed 1235 F34.0 Figure 35:Wait Options Flowchart (PP Mode) ©2011 Silicon Storage Technology, Inc.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Software Product ID Entry Command Sequence Software Product ID Exit Command Sequence Write data: AAH Address: 5555H Write data: AAH Address: 5555H Write data: F0H Address: XXH Write data: 55H Address: 2AAAH Write data: 55H Address: 2AAAH Wait TIDA Write data: 90H Address: 5555H Write data: F0H Address: 5555H Return to normal operation Wait TIDA Wait TIDA Read Software ID Return to normal operation 1235 F35.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Chip-Erase Command Sequence Block-Erase Command Sequence Sector-Erase Command Sequence Write data: AAH Address: 5555H Write data: AAH Address: 5555H Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 55H Address: 2AAAH Write data: 55H Address: 2AAAH Write data: 80H Address: 5555H Write data: 80H Address: 5555H Write data: 80H Address: 5555H Write data: AAH Address: 5555H Write data: AAH Address: 555
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Product Ordering Information SST 49 LF XX XX 080A XXXX - 33 XX - 4C XX - NHE XXX Environmental Attribute E1 = non-Pb Package Modifier H = 32 leads Package Type N = PLCC W = TSOP (type 1, die up, 8mm x 14mm) Operating Temperature C = Commercial = 0°C to +85°C Minimum Endurance 4 = 10,000 cycles Serial Access Clock Frequency 33 = 33 MHz Version Device Density 080 = 8 Mbit Voltage Range L = 3.0-3.6V 1.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Packaging Diagrams TOP VIEW Optional Pin #1 Identifier .048 .042 .495 .485 .453 .447 2 1 32 SIDE VIEW .112 .106 .020 R. .029 x 30° MAX. .023 .040 R. .030 .042 .048 .595 .553 .585 .547 BOTTOM VIEW .021 .013 .400 .530 BSC .490 .032 .026 .050 BSC .015 Min. .095 .075 .050 BSC .140 .125 .032 .026 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet 1.05 0.95 Pin # 1 Identifier 0.50 BSC 8.10 7.90 0.27 0.17 0.15 0.05 12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80 0°- 5° 0.70 0.50 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 32-tsop-WH-7 1mm 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.
8 Mbit LPC Flash SST49LF080A A Microchip Technology Company Data Sheet Table 26:Revision History Revision Description 00 • 01 • 02 • • • • • • • A Date Initial release (SST49LF080A previously released in data sheet S71206) Added statement that non-Pb devices are RoHS compliant to Features section Updated Surface Mount Solder Reflow Temperature information Added footnote to Product Ordering Information section Removed leaded part numbers Updated Table 5 on page 11 Applied new document format Rel