Datasheet

©2011 Silicon Storage Technology, Inc. DS25029A 06/11
29
16 Mbit LPC Serial Flash
SST49LF016C
Data Sheet
A
Microchip Technology Company
AAI Data Load Protocol
Figure 9: AAI Load Protocol Waveform
Table 19:AAI Programming Cycle (initiated with WP#/AAI at V
H
ONLY)
Clock
Cycle
Field Name Field Contents LAD[3:0] Comments
1 START 1110 IN LFRAME# must be active (low) for the part to respond.
Only the last start field (before LFRAME# transitions
high) should be recognized. The START field contents
indicate a Firmware Memory Write cycle. (1110b)
2 IDSEL 0000b to 1111b IN ID works identically to Firmware Memory cycle.
This field indicates which SST49LF016C device
should respond. If the IDSEL (ID select) field matches
the value of ID[3:0], then that particular device will
respond to the whole bus cycle.
3-9 MADDR YYYY IN These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
Only bits [20:7] of the total address [27:0] are used for
AAI mode. The rest are “don’t care”.
10 MSIZE KKKK IN MSIZE field is don’t care when in AAI mode
11-266 DATA ZZZZ IN Data is transmitted to the device least significant nib-
ble first, from byte 0 to byte 127 as long as the RY/BY#
is high and LD# low. The host will pause the clock and
data stream when RY/BY# goes low until it returns
high, signifying that the chip is ready for more data
T19.0 25029
1 2 3 4 5 6 7 8 9 10 11 12 266264
WP#/AAI
LAD[3:0]
LCLK
(Data Strobe Input)
LD#
V
H
LFRAME#
RY/BY#
Start
IDSEL
MSIZE
MADDR
Address
Byte 0 Byte N
Byte
N+1
Byte
2N
Byte
126
Byte
127
DATA D ATA DATADA TA
DA TA DAT A
1237 F08.1