Datasheet

16 Mbit LPC Serial Flash

SST49LF016C

Data Sheet

Microchip Technology Company

Block Locking Registers

SST49LF016C provides software controlled lock protection through a set of Block Locking registers.

The Block Locking Registers are read/write registers and they are accessible through standard

addressable memory locations specified in Table 14. Unused register locations will return 00H if read.

In case of multi-byte register reads with Firmware Memory cycle, the device will return register data for

the addressed register until the command finishes, or is aborted.

Table 13:Multi-byte Read/Write Configuration Registers (Firmware Memory Cycle Only)

Address

Data Access Description

MULTI_BYTE_READ_L FFBC 0005H 0100 1011b R Device supports 1,2,4, 16, 128 Byte reads

MULTI_BYTE_READ_H FFBC 0006H 0000 0000b R Future Expansion for Read

MULTI_BYTE_WRITE_L FFBC 0007H 0000 0011b R Device supports 1, 2, 4 Byte Write

MULTI_BYTE_WRITE_H FFBC 0008H 0000 0000b R Future Expansion for Write

T13.0 25029

1. Address shown in this column is for boot device only. Address locations should appear elsewhere in the 4 GByte sys-

tem memory map depending on ID strapping values on ID[3:0] pins when multiple LPC memory devices are used in a

system.