Datasheet
©2011 Silicon Storage Technology, Inc. DS25029A 06/11
13
16 Mbit LPC Serial Flash
SST49LF016C
Data Sheet
A
Microchip Technology Company
Firmware Memory Write Cycle
Figure 7: Firmware Memory Write Cycle Waveform
Table 5: Firmware Memory Write Cycle
Clock
Cycle
Field
Name
Field
Contents
LAD[3:0]
1
1. Field contents are valid on the rising edge of the present clock cycle.
LAD[3:0]
Direction Comments
1 START 1110 IN LFRAME# must be active (low) for the part to respond. Only the
last start field (before LFRAME# transitions high) will be recog-
nized. The START field contents (1110b) indicate a Firmware
Memory Write cycle.
2 IDSEL 0000 to
1111
IN Indicates which SST49LF016C device should respond. If the
IDSEL (ID select) field matches the value of ID[3:0], then that par-
ticular device will respond to the whole bus cycle.
3-9 MADDR YYYY IN These seven clock cycles make up the 28-bit memory address.
YYYY is one nibble of the entire address. Addresses are trans-
ferred most-significant nibble first.
10 MSIZE KKKK IN The MSIZE field indicates how many bytes will be transferred
during multi-byte operations.
Device supports 1, 2, and 4 Bytes write with MSIZE = 0, 1, or 2,
and KKKK=0000b, 0001b, or 0010b.
11-A DATA ZZZZ IN A=(10+2
n+1
); n = MSIZE
Least significant nibble entered first.
(A+1) TAR0 1111 IN then
Float
In this clock cycle, the master has driven the bus to all ‘1’s and
then floats the bus prior to the next clock cycle. This is the first part
of the bus “turnaround cycle.” A=(10+2
n+1
); n = MSIZE
(A+2) TAR1 1111
(float)
Float
then OUT
The SST49LF016C takes control of the bus during this cycle.
A=(10+2
n+1
); n = MSIZE
(A+3) RSYNC 0000 OUT During this clock cycle, the SST49LF016C generates a “ready
sync” (RSYNC) and outputs the values 0000, indicating that it has
received data or a flash command. A=(10+2
n+1
); n = MSIZE
(A+4) TAR0 1111 OUT then
Float
In this clock cycle, the SST49LF016C drives the bus to all ‘1’s and
then floats the bus prior to the next clock cycle. This is the first part
of the bus “turnaround cycle”. A=(10+2
n+1
); n = MSIZE
(A+5) TAR1 1111
(float)
Float
then IN
The host resumes control of the bus during this cycle.
A=(10+2
n+1
); n = MSIZE
T5.0 25029
1237 F04.0
LFRAME#
LAD[3:0]
1110b 0000b A[23:20]
A[19:16]
A[3:0]A[7:4]A[11:8]A[15:12]
MADDRStart IDSEL
MSIZE
LCLK
A[27:24] 0000b
RSYNC
TAR1TAR0
TA RD
0
[7:4] Tri-StateD
0
[3:0] Dn[7:4]Dn[3:0]KKKKb 1111b
DA TA