Datasheet

©2011 Silicon Storage Technology, Inc. DS25029A 06/11
12
16 Mbit LPC Serial Flash
SST49LF016C
Data Sheet
A
Microchip Technology Company
Firmware Memory Cycles
Firmware Memory Read Cycle
Figure 6: Firmware Memory Read Cycle Waveform
Table 4: Firmware Memory Read Cycle Field Definitions
Clock
Cycle
Field
Name
Field
Contents
LAD[3:0]
1
1. Field contents are valid on the rising edge of the present clock cycle.
LAD[3:0]
Direction Comments
1 START 1101 IN LFRAME# must be active (low) for the part to respond. Only the last
start field (before LFRAME# transitions high) will be recognized. The
START field contents (1101b) indicate a Firmware Memory Read
cycle.
2 IDSEL 0000 to
1111
IN Indicates which SST49LF016C device should respond. If the
IDSEL (ID select) field matches the value of ID[3:0], then that par-
ticular device will respond to the LPC bus cycle.
3-9 MADD
R
YYYY IN These seven clock cycles make up the 28-bit memory address.
YYYY is one nibble of the entire address. Addresses are trans-
ferred most-significant nibble first.
10 MSIZE KKKK IN The MSIZE field indicates how many bytes will be transferred dur-
ing multi-byte operations.
Device will execute multi-byte read of 2
MSIZE
bytes. SST49LF016C
supports only MSIZE = 0, 1, 2, 4, 7 (1, 2, 4, 16, 128 Bytes), with
KKKK=0000b, 0001b, 0010b, 0100b, or 0111b.
11 TAR0 1111 IN,
then Float
In this clock cycle, the master has driven the bus to all ‘1’s and then
floats the bus, prior to the next clock cycle. This is the first part of the
bus “turnaround cycle.”
12 TAR1 1111 (float) Float,
then OUT
The SST49LF016C takes control of the bus during this cycle.
13 RSYN
C
0000
(READY)
OUT During this clock cycle, the device generates a “ready sync”
(RSYNC) indicating that the device has received the input data.
The least-significant nibble of the least-significant byte will be
available during the next clock cycle.
14-A DATA ZZZZ OUT A=(13+2
n+1
); n = MSIZE. Least significant nibbles outputs first.
(A+1) TAR0 1111 OUT,
then Float
In this clock cycle, the SST49LF016C drives the bus to all ones
and then floats the bus prior to the next clock cycle. This is the first
part of the bus “turnaround cycle.” A=(13+2
n+1
); n = MSIZE
(A+2) TAR1 1111 (float) Float,
then IN
The host resumes control of the bus during this cycle.
A=(13+2
n+1
); n = MSIZE
T4.0 25029
1237 F03.0
LFRAME#
LAD[3:0]
1101b 0000b A[23:20] A[19:16] A[3:0]A[7:4]A[11:8]A[15:12]
MADDRStart IDSEL
MSIZE
LCLK
A[27:24] 0000b
RSYNC
TAR1TAR0
TA RD
0
[7:4]Tri-State D
0
[3:0] D
n
[7:4]D
n
[3:0]KKKKb 1111b
DA TA