Datasheet

16 Mbit LPC Serial Flash

SST49LF016C

Data Sheet

Microchip Technology Company

LPC Mode

Device Operation

The SST49LF016C supports Multi-Byte Firmware Memory Read and Write cycle types as defined in

Low Pin Count Interface Specification, Revision 1.1. Table 2 shows the size of transfer supported by

the SST49LF016C.

The LPC mode uses a 5-signal communication interface: one control line, LFRAME#, which is driven

by the host to start or abort a bus cycle, a 4-bit data bus, LAD[3:0], used to communicate cycle type,

cycle direction, ID selection, address, data and sync fields. The device enters standby mode when

LFRAME# is taken high and no internal operation is in progress.

The host drives LFRAME# signal from low-to-high to capture the start field of a LPC cycle. On the

cycle in which LFRAME# goes inactive, the last latched value is taken as the START value. The START

value determines whether the SST49LF016C will respond to a Firmware Memory Read/Write cycle

type as defined in Table 3.

See following sections on details of Firmware Memory cycle types (Tables 4 and 5). Two-cycle Program

and Erase command sequences are used to initiate Firmware Memory Program and Erase operations. See

Table 8 for a listing of Program and Erase commands.

Table 2: Transfer Size Supported

Cycle Type Size of Transfer

Firmware Memory Read 1, 2, 4, 16, 128 Bytes

Firmware Memory Write 1, 2, 4 Bytes

T2.1 25029

Table 3: Firmware Memory Cycles START Field Definition

START Value Definition

1101 Start of a Firmware Memory Read cycle

1110 Start of a Firmware Memory Write cycle

T3.1 25029