6 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet The SST49LF016C flash memory device is designed to interface with host controllers (chipsets) that support a low pin-count (LPC) interface for system firmware applications. Complying with LPC Interface Specification 1.1, SST49LF016C supports a Burst-Read data transfer of 15.6 MBytes per second at 33 MHz clock speed and 31.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Product Description The SST49LF016C flash memory device is designed to interface with host controllers (chipsets) that support a low-pin-count (LPC) interface for system firmware applications. Complying with LPC Interface Specification 1.1, SST49LF016C supports a Burst-Read data transfer of 15.6 MBytes per second at 33 MHz clock speed and 31.2 MBytes per second at 66 MHz clock speed, up to 128 bytes in a single operation.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Functional Blocks TBL# WP# INIT# X-Decoder SuperFlash Memory LAD[3:0] LCLK LFRAME# LPC Interface Address Buffers & Latches Y-Decoder ID[3:0] GPI[4:0] AAI Control Logic I/O Buffers and Data Latches AAI Interface RY/BY# LD# RST# 1237 B1.0 Figure 1: Functional Block Diagram ©2011 Silicon Storage Technology, Inc.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Device Memory Map 1FFFFFH Block 34 11FFFFH Block 17 Boot Block 1FC000H 1FBFFFH 110000H 10FFFFH Block 33 Block 16 1FA000H 1F9FFFH 100000H 0FFFFFH Block 32 Block 15 1F8000H 1F7FFFH 0F0000H 0EFFFFH Block 31 Block 14 1F0000H 1EFFFFH 0E0000H 0DFFFFH Block 30 Block 13 1E0000H 1DFFFFH Block 29 Block 12 1D0000H 1CFFFFH Block 28 Block 27 WP# for Block 0 33 Block 26 Block 25 Block 24 Block 23 Block 22 Block 21 Block 2
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet NC 2 1 GPI4 RST# 3 LCLK GPI3 4 NC GPI2 Pin Assignments NC 6 28 NC WP#/AAI 7 27 NC TBL# 8 26 NC ID3 9 25 VDD ID2 10 24 INIT# ID1 11 23 LFRAME# ID0 12 22 NC LAD0 13 21 14 15 16 17 18 19 20 NC NC NC LAD3 ( ) Designates AAI Mode VSS 32-lead PLCC Top View LAD2 GPI0 (RY/BY#) LAD1 5 NC 32 31 30 29 GPI1 (LD#) 1237 32-plcc P2.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet NC NC NC NC NC NC GPI4 NC LCLK NC NC RST# NC NC GPI3 GPI2 GPI1 (LD#) GPI0 (RY/BY#) WP#/AAI TBL# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40-lead TSOP Top View 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 NC VDD LFRAME# INIT# NC NC NC NC NC NC VSS VSS LAD3 LAD2 LAD1 LAD0 ID0 ID1 ID2 ID3 ( ) Designates AAI Mode 1237 40-tsop P3.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Pin Descriptions Table 1: Pin Description Interface Type1 AAI LPC Functions I X X To accept a clock input from the control unit I/O X X To provide LPC bus information, such as addresses and command Inputs/Outputs data. I X X To indicate the start of a data transfer operation; also used to abort an LPC cycle in progress. I X X To reset the operation of the device I X X This is the second reset pin for in-system use.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Clock The LCLK pin accepts a clock input from the host controller. Input/Output Communications The LAD[3:0] pins are used to serially communicate cycle information such as cycle type, cycle direction, ID selection, address, data, and sync fields. Input Communication Frame The LFRAME# pin is used to indicate start of a LPC bus cycle. The pin is also used to abort an LPC bus cycle in progress.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Write Protect / Top Block Lock The Top Boot Lock (TBL#) and Write Protect (WP#/AAI) pins are provided for hardware write protection of device memory in the SST49LF016C. The TBL# pin is used to write protect 16 KByte at the highest memory address range for the SST49LF016C. WP#/AAI pin write protects the remaining sectors in the flash memory.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Design Considerations SST recommends a high frequency 0.1 µF ceramic capacitor to be placed as close as possible between VDD and VSS less than 1 cm away from the VDD pin of the device. Additionally, a low frequency 4.7 µF electrolytic capacitor from VDD to VSS should be placed within 1 cm of the VDD pin. If you use a socket for programming purposes add an additional 1-10 µF next to each socket.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet LPC Mode Device Operation The SST49LF016C supports Multi-Byte Firmware Memory Read and Write cycle types as defined in Low Pin Count Interface Specification, Revision 1.1. Table 2 shows the size of transfer supported by the SST49LF016C. Table 2: Transfer Size Supported Cycle Type Size of Transfer Firmware Memory Read 1, 2, 4, 16, 128 Bytes Firmware Memory Write 1, 2, 4 Bytes T2.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Firmware Memory Cycles Firmware Memory Read Cycle Table 4: Firmware Memory Read Cycle Field Definitions Field Contents LAD[3:0]1 1101 Clock Cycle 1 Field Name START 2 IDSEL 0000 to 1111 3-9 MADD R YYYY 10 MSIZE KKKK 11 TAR0 1111 12 TAR1 1111 (float) 13 RSYN C 0000 (READY) 14-A (A+1) DATA TAR0 ZZZZ 1111 (A+2) TAR1 1111 (float) LAD[3:0] Direction Comments IN LFRAME# must be active (low) for the part to
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Firmware Memory Write Cycle Table 5: Firmware Memory Write Cycle Clock Cycle Field Name Field Contents LAD[3:0]1 1 START 1110 IN LFRAME# must be active (low) for the part to respond. Only the last start field (before LFRAME# transitions high) will be recognized. The START field contents (1110b) indicate a Firmware Memory Write cycle. 2 IDSEL 0000 to 1111 IN Indicates which SST49LF016C device should respond.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Abort Mechanism If LFRAME# is driven low for one or more clock cycles after the start of a bus cycle, the cycle will be terminated. The host may drive the LAD[3:0] with ‘1111b’ (ABORT nibble) to return the interface to ready mode. The ABORT only affects the current bus cycle.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Non-boundary-aligned address: The SST49LF016C accepts multi-byte transfers for both Read and Write operations. The device address space is divided into uniform page sizes 2, 4, 16, or 128 bytes wide, according to the MSIZE value (see Table 6). The host issues only one address in the MADDR field of the Firmware Memory Cycle, but multiple bytes are read from or written to the device.
Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Device Commands Device operation is controlled by commands written to the Command User Interface (CUI). Execution of a specific command is handled by internal functions after a CUI receives and processes the command. After power-up or a Reset operation the device enters Read mode. Commands consist of one or two sequential Bus-Write operations. The commands are summarized in Table 8, “Software Command Sequence”.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Read-Array Command Upon initial device power-up and after exit from reset, the device defaults to the read array mode. This operation can also be initiated by writing the Read-Array command. (See Table 8.) The device remains available for array reads until another command is written.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Clear-Status-Register Command The user can reset the Status register’s Block Protect Status (BPS) bit to 0 by issuing a Clear-StatusRegister command. Device power-up and hardware reset will also reset BPS to 0. Table 10:Software Status Register Bit Name Function 0 RES Reserved for future use 1 BPS Block Protect Status The Block Write-Lock bit should be interrogated only after Erase or Program command is issued.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Erase-Suspend/Erase-Resume Commands The Erase Suspend command allows Sector-Erase or Block-Erase interruption in order to read or program data in another block of memory. Once the Erase-Suspend command is executed, the device will suspend any on-going Erase operation within time TES (10 µs). The device outputs status register data when read after the Erase-Suspend command is written.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Erase Sector/Block Write B0H to any valid device memory address Erase-Suspend Command Write 70H to any valid device memory address Read-Status-Register Command Read Status Register No WSMS = 1 Yes ESS = 1 Erase Completed No Yes Write the Read-Array command to read from another Sector/Block or Write the Program command to program another Sector/Block No Finished Yes Write D0H to any valid device memory address Erase-
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Registers There are five types of registers available on the SST49LF016C, the multi-byte Read/Write configuration registers (for Firmware Memory cycle), General Purpose Inputs registers, Block Locking registers, Security ID register, and the JEDEC ID registers. These registers appear at their respective address location in the 4 GByte system memory map. Unused register locations will read as 00H.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Table 13:Multi-byte Read/Write Configuration Registers (Firmware Memory Cycle Only) Register Address1 Data MULTI_BYTE_READ_L FFBC 0005H 0100 1011b R Device supports 1,2,4, 16, 128 Byte reads MULTI_BYTE_READ_H FFBC 0006H 0000 0000b R Future Expansion for Read MULTI_BYTE_WRITE_L FFBC 0007H 0000 0011b R Device supports 1, 2, 4 Byte Write MULTI_BYTE_WRITE_H FFBC 0008H 0000 0000b R Future Expansion for Write R
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Table 14:Block Locking Registers Register SST49LF016C Protected Memory Block Size Address1 Range Memory Map Register Address1 T_BLOCK_LK 16K 1FFFFFH-1FC000H FFBFC002H T_MINUS01_LK 8K 1FBFFFH-1FA000H FFBFA002H T_MINUS02_LK 8K 1F9FFFH-1F8000H FFBF8002H T_MINUS03_LK 32K 1F7FFFH-1F0000H FFBF0002H T_MINUS04_LK 64K 1EFFFFH-1E0000H FFBE0002H T_MINUS05_LK 64K 1DFFFFH-1D0000H FFBD0002H T_MINUS06_LK 64K 1CFF
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Table 15:Block Locking Register Bits Reserved Bit Read-Lock Bit Lock-Down Bit Write-Lock Bit [7:3] [2] [1] [0] Lock Status 00000 0 0 0 Full Access 00000 0 0 1 Write Locked (Default State at Power-Up) 00000 0 1 0 Locked Open (Full Access Locked Down) 00000 0 1 1 Write Locked Down 00000 1 0 0 Block Read Locked (Registers alterable) 00000 1 0 1 Block Read & Write Lock (Registers alterable) 00000 1
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Security ID Registers The SST49LF016C device offers a 256-bit Security ID register space. The Security ID space is divided into two segments - one (64-bits) factory programmed segment and one (192 bits) user programmed segment. The first segment is programmed and locked at SST with a unique 64-bit number. The user segment (192 bits) is left blank (FFH) for the customer to be programmed as desired.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet JEDEC ID Registers The JEDEC ID registers for the boot device appear at FFBC0000H and FFBC0001H in the 4 GByte system memory map, and will appear elsewhere if the device is not the boot device. This register is not available to be read when the device is in Erase/Program operation. Unused register location will read as 00H. See Table 17 for the JEDEC device ID code.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Auto-Address Increment (AAI) MODE AAI Mode with Multi-byte Programming AAI mode with multi-byte programming is provided for high-speed production programming. AutoAddress Increment mode requires only one address load for each 128-byte page of data. Taking the WP#/AAI pin to the Supervoltage VH enables the AAI mode. The AAI command is started as a normal Firmware Memory cycle.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Table 18:LD# Input and RY/BY# Status in AAI Mode LD# state RY/BY# status RY/BY# Flag indication L H Device is Ready, can accept more data until the last (128th) byte. L L Device is Busy, cannot accept more data L H Device is Ready for next operation if previous data is the last (128th) byte. H H Device is Ready for next operation H L Device is Busy programming T18.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet AAI Data Load Protocol Table 19:AAI Programming Cycle (initiated with WP#/AAI at VH ONLY) Clock Cycle Field Name Field Contents LAD[3:0] Comments 1 START 1110 IN LFRAME# must be active (low) for the part to respond. Only the last start field (before LFRAME# transitions high) should be recognized. The START field contents indicate a Firmware Memory Write cycle.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Electrical Specifications The AC and DC specifications for the LPC interface signals (LAD[3:0], LFRAME#, LCLCK and RST#) as defined in Section 4.2.2.4 of the PCI local Bus specification, Rev. 2.1. Refer to Table 22 for the DC voltage and current specifications. Refer to Table 26 through Table 28 for the AC timing specifications for Clock, Read, Write, and Reset operations.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet DC Characteristics Table 22:DC Operating Characteristics at 33 MHz and 66 MHz (All Interfaces) Limits Symbo l Parameter IDD1 Min Max Unit s Active VDD Current Test Conditions LCLK (LPC mode)=VILT/VIHT All other inputs=VIL or VIH Read 18 mA All outputs = open, VDD=VDD Max Single-/Dual-Byte Program, Erase 40 mA Quad-Byte Program 60 mA ISB Standby VDD Current (LPC Interface) 100 µA LCLK (LPC mode)=VILT/VIHT at
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Table 24:Pin Capacitance (VDD=3.3V, TA=25 °C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum CI/O1 I/O Pin Capacitance VI/O=0V 12 pF CIN Input Capacitance VIN=0V LPIN2 Pin Inductance 1 12 pF 20 nH T24.0 25029 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. Refer to PCI spec.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Table 27:Reset Timing Parameters, VDD=3.0-3.6V (LPC Mode) Parameter Min TPRST Symbol VDD stable to Reset High 100 TRSTP RST# Pulse Width 100 TRSTF RST# Low to Output Float TRST 1 Units µs ns 48 RST# High to LFRAME# Low 5 RST# Low to reset during Sector-/Block-Erase or Program TRSTE Max ns LCLK cycles 10 µs T27.0 25029 1.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet AC Characteristics Table 28:Read/Write Cycle Timing Parameters, VDD=3.0-3.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet VTH VTEST LCLK VTL TVAL LAD [3:0] (Valid Output Data) LAD [3:0] (Float Output Data) TON TOFF 1237 F11.0 Figure 12:Output Timing parameters (LPC Mode) VTH LCLK VTEST VTL TSU TDH LAD [3:0] (Valid Input Data) Inputs Valid VMAX 1237 F12.0 Figure 13:Input Timing Parameters (LPC Mode) Table 30:Interface Measurement Condition Parameters (LPC Mode) Symbol Value Units 1 0.6 VDD V VTL1 0.2 VDD V VTEST 0.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet VH WP#/AAI TACYC VTH VTL VTEST LCLK TASU TADH LAD [3:0] (Valid Input Data) VMAX Inputs Valid TLDSU TLDDH LD# TRB RY/BY# 1237 F13.3 Figure 14:Input Timing Parameters (AAI Mode) Table 31:Input Cycle Timing Parameters, VDD=3.0-3.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1237 F14.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <3 ns.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Product Ordering Information SST 49 LF XX XX 016 XXX - 33 XX - 4C XX - NHE XXX Environmental Attribute E1 = non-Pb Package Modifier H = 32 leads I = 40 leads Package Type N = PLCC W = TSOP (type 1, die up, 8mm x 14mm) E = TSOP (type 1, die up, 10mm x 20mm) Temperature Range C = Commercial = 0°C to +85°C Minimum Endurance 4 = 10,000 cycles Operating Frequency 33 = 33 MHz 66 = 66 MHz Device Density 016 = 16 Mbit Voltage L
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Packaging Diagrams TOP VIEW Optional Pin #1 Identifier .048 .042 .495 .485 .453 .447 2 1 32 SIDE VIEW .112 .106 .020 R. .029 x 30° MAX. .023 .040 R. .030 .042 .048 .595 .553 .585 .547 BOTTOM VIEW .021 .013 .400 .530 BSC .490 .032 .026 .050 BSC .015 Min. .095 .075 .050 BSC .140 .125 .032 .026 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet 1.05 0.95 Pin # 1 Identifier 0.50 BSC 8.10 7.90 0.27 0.17 0.15 0.05 12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80 0°- 5° 0.70 0.50 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 32-tsop-WH-7 1mm 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet 1.05 0.95 Pin # 1 Identifier 0.50 BSC 0.27 0.17 10.10 9.90 0.15 0.05 18.50 18.30 DETAIL 1.20 max. 0.70 0.50 20.20 19.80 0°- 5° Note: 1. Complies with JEDEC publication 95 MO-142 CD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 0.70 0.
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet Table 32:Revision History Revision 00 01 02 03 04 Description • • • • • • • • • • • • • • 07 • • • 08 • A • • • 05 06 Date S71237(01): Initial release of fact sheet (Advance Information) S71237(01): Fact sheet changes 2004 Flash Data Book S71237(01): Fact sheet synchronized to and integrated into full data sheet S71237: Initial release of data sheet (Advance Information) Added Auto-Address Increment (AAI) mode Add
16 Mbit LPC Serial Flash SST49LF016C A Microchip Technology Company Data Sheet ISBN:978-1-61341-324-1 © 2011 Silicon Storage Technology, Inc–a Microchip Technology Company. All rights reserved. SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc.