Datasheet

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Microchip Technology Company

ping and paging, please refer to the Intel 82801(ICH) I/O Controller Hub documentation. Since there is

no ID support in PP Mode, to program multiple devices a stand-alone PROM programmer is recom-

mended.

Registers

There are three types of registers available on the SST49LF008A, the General Purpose Inputs regis-

ter, Block Locking registers and the JEDEC ID registers. These registers appear at their respective

address location in the 4 GByte system memory map. Unused register locations will read as 00H.

Attempts to read or write to any registers during internal Write operations will be ignored.

General Purpose Inputs Register

The GPI_REG (General Purpose Inputs Register) passes the state of FGPI[4:0] pins at power-up on

the SST49LF008A. It is recommended that the FGPI[4:0] pins are in the desired state before FWH4 is

brought low for the beginning of the bus cycle, and remain in that state until the end of the cycle. There

is no default value since this is a pass-through register. The GPI register for the boot device appears at

FFBC0100H in the 4 GByte system memory map, and will appear elsewhere if the device is not the

boot device. Register is not available for read when the device is in Erase/Program operation. See

Table 5 for the GPI_REG bits and function.

Table 5: General Purpose Inputs Register

Bit Function

Pin #

32-PLCC 32-TSOP 40-TSOP

7:5 Reserved - - -

4 FGPI[4]

Reads status of general

purpose input pin

30 6 7

3 FGPI[3]

Reads status of general

purpose input pin

31115

2 FGPI[2]

Reads status of general

purpose input pin

41216

1 FGPI[1]

Reads status of general

purpose input pin

51317

0 FGPI[0]

Reads status of general

purpose input pin

61418

T5.3 25085