8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet The SST49LF008A flash memory devices are designed to be read-compatible with the Intel® 82802 Firmware Hub (FWH) device for PC-BIOS application. These devices provide protection for the storage and update of code and data in addition to adding system design flexibility through five general purpose inputs.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Product Description The SST49LF008A flash memory devices are designed to be read-compatible with the Intel® 82802 Firmware Hub (FWH) device for PC-BIOS application. These devices provide protection for the storage and update of code and data in addition to adding system design flexibility through five general purpose inputs.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Functional Block Diagram TBL# WP# INIT# X-Decoder SuperFlash Memory FWH[3:0] CLK FWH4 FWH Interface Address Buffers Latches Y-Decoder ID[3:0] FGPI[4:0] R/C# A[10:0] DQ[7:0] Control Logic I/O Buffers and Data Latches Programmer Interface OE# WE# IC RST# 1161 B1.2 Figure 1: Functional Block Diagram ©2011 Silicon Storage Technology, Inc.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Pin Assignments NC NC NC VSS (VSS) IC (IC) A10 (FGPI4) R/C# (CLK) VDD (VDD) NC RST# (RST#) A9 (FGPI3) A8 (FGPI2) A7 (FGPI1) A6 (FGPI0) A5 (WP#) A4 (TBL#) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Standard Pinout Top View Die Up OE# (INIT#) WE# (FWH4) VDD (VDD) DQ7 (RES) DQ6 (RES) DQ5 (RES) DQ4 (RES) DQ3 (FWH3) VSS (VSS) DQ2 (FWH2) DQ1 (FWH1) DQ0 (FWH0) A0 (ID0) A1 (ID1) A2 (ID2) A3
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet NC (NC) IC (IC) NC (NC) NC (NC) NC (NC) NC (NC) A10 (FGPI4) NC (NC) R/C# (CLK) VDD NC (NC) RST# (RST#) NC (NC) NC (NC) A9 (FGPI3) A8 (FGPI2) A7 (FGPI1) A6 (FGPI0) A5 (WP#) A4 (TBL#) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Standard Pinout Top View Die Up ( ) Designates FWH Mode 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS VDD (FWH4) WE# (INIT#) OE# (NC) NC (RES) DQ7 (RES) DQ6 (RES) DQ5 (RES) DQ4 (N
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Table 1: Pin Description Interface Symbol A10-A0 Pin Name Address DQ7-DQ0 Data Type1 PP FWH Functions I X Inputs for low-order addresses during Read and Write operations. Addresses are internally latched during a Write cycle. For the programming interface, these addresses are latched by R/ C# and share the same pins as the high-order address inputs.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Device Memory Map 0FFFFFH Block 15 TBL# Boot Block 0F0000H 0EFFFFH Block 14 0E0000H 0DFFFFH Block 13 0D0000H 0CFFFFH Block 12 0C0000H 0BFFFFH Block 11 0B0000H 0AFFFFH Block 10 0A0000H 09FFFFH Block 9 090000H 08FFFFH Block 8 WP# for Block 0 14 080000H 07FFFFH Block 7 070000H 06FFFFH Block 6 060000H 05FFFFH Block 5 050000H 04FFFFH Block 4 040000H 03FFFFH Block 3 030000H 02FFFFH Block 2 020000H 01FFFFH Block 1 Block 0 (64 KByte)
Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Design Considerations SST recommends a high frequency 0.1 µF ceramic capacitor to be placed as close as possible between VDD and VSS less than 1 cm away from the VDD pin of the device. Additionally, a low frequency 4.7 µF electrolytic capacitor from VDD to VSS should be placed within 1 cm of the VDD pin. If you use a socket for programming purposes add an additional 1-10 µF next to each socket.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Firmware Hub (FWH) Mode Device Operation The FWH mode uses a 5-signal communication interface, FWH[3:0] and FWH4, to control operations of the SST49LF008A. Operations such as Memory Read and Memory Write uses Intel FWH propriety protocol. JEDEC Standard SDP (Software Data Protection) Byte-Program, Sector-Erase and BlockErase command sequences are incorporated into the FWH memory cycles. Chip-Erase is only available in PP Mode.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Table 3: FWH Read Cycle Clock Cycle Field Name Field Contents FWH[3:0] FWH[3:0]1 Direction Comments 1 START 1101 IN FWH4 must be active (low) for the part to respond. Only the last start field (before FWH4 transitions high) should be recognized. The START field contents indicate a FWH memory Read cycle. 2 IDSEL 0000 to 1111 IN Indicates which FWH device should respond.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Table 4: FWH Write Cycle Clock Cycle Field Name Field Contents FWH[3:0]1 FWH[3:0] Direction 1 START 1110 IN FWH4 must be active (low) for the part to respond. Only the last start field (before FWH4 transitions high) should be recognized. The START field contents indicate a FWH memory Read cycle. 2 IDSEL 0000 to 1111 IN Indicates which SST49LF008A device should respond.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Abort Mechanism If FWH4 is driven low for one or more clock cycles during a FWH cycle, the cycle will be terminated and the device will wait for the ABORT command. The host may drive the FWH[3:0] with ‘1111b’ (ABORT command) to return the device to Ready mode. If abort occurs during a Write operation, the data may be incorrectly altered.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Reset A VIL on INIT# or RST# pin initiates a device reset. INIT# and RST# pins have the same function internally. It is required to drive INIT# or RST# pins low during a system reset to ensure proper CPU initialization. During a Read operation, driving INIT# or RST# pins low deselects the device and places the output drivers, FWH[3:0], in a high-impedance state.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet ping and paging, please refer to the Intel 82801(ICH) I/O Controller Hub documentation. Since there is no ID support in PP Mode, to program multiple devices a stand-alone PROM programmer is recommended. Registers There are three types of registers available on the SST49LF008A, the General Purpose Inputs register, Block Locking registers and the JEDEC ID registers.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Block Locking Registers SST49LF008A provides software controlled lock protection through a set of Block Locking registers. The Block Locking Registers are read/write registers and it is accessible through standard addressable memory locations specified in Table 6. Unused register locations will read as 00H.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Write Lock The Write-Lock bit, bit 0, controls the lock state described in Table 7. The default Write status of all blocks after power-up is write locked. When bit 0 of the Block Locking register is set, Program and Erase operations for the corresponding block are prevented. Clearing the Write-Lock bit will unprotect the block.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Parallel Programming Mode Device Operation Commands are used to initiate the memory operation functions of the device. The data portion of the software command sequence is latched on the rising edge of WE#. During the software command sequence the row address is latched on the falling edge of R/C# and the column address is latched on the rising edge of R/C#. Reset A VIL on RST# pin initiates a device reset.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Sector-Erase Operation The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The Sector-Erase operation is initiated by executing a six-byte command load sequence for Software Data Protection with Sector-Erase command (30H) and sector address (SA) in the last bus cycle.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Write Operation Status Detection The SST49LF008A device provides two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE# which initiates the internal Program or Erase operation.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Table 8: Operation Modes Selection (PP Mode) Mode RST# OE# WE# DQ Erase VIH VIH VIH VIL VIH VIH Reset VIL X Write Inhibit VIH X VIH VIL Read Program Product Identification Address VIH DOUT AIN VIL DIN AIN VIL X1 Sector or Block address, XXH for ChipErase X High Z X VIL X High Z/DOUT X X VIH VIH High Z/DOUT X Manufacturer’s ID (BFH) A18-A1=VIL, A0=VIL Device ID2 A18-A1=VIL, A0=VIH T8.6 25085 1.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Software Command Sequence Table 9: Software Command Sequence 1st1 Write Cycle Command Sequence 2nd1 Write Cycle Addr2 Data Addr2 3rd1 Write Cycle Data Addr2 4th1 Write Cycle Data Addr2 BA3 5th1 Write Cycle Data Addr2 6th1 Write Cycle Data Addr2 Data Data Byte-Program 5555H AAH 2AAAH 55H 5555H A0H Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX4 30H Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 55
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Electrical Specifications The AC and DC specifications for the FWH Interface signals (FWH[3:0], CLK, FWH4, and RST#) as defined in Section 4.2.2 of the PCI Local Bus Specification, Rev. 2.1. Refer to Table 12 for the DC voltage and current specifications. Refer to the tables on pages 24 through 29 for the AC timing specifications for Clock, Read/Write, and Reset operations.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet DC Characteristics Table 12:DC Operating Characteristics (All Interfaces) Limits Symbol Parameter IDD Active VDD Current Min Max Unit s Test Conditions1 LCLK (FWH mode) and Address Input (PP mode)=VILT/VIHT at f=33 MHz (FWH mode) or 1/TRC min (PP Mode) All other inputs=VIL or VIH ISB Read 12 mA All outputs = open, VDD=VDD Max Write2 24 mA See Note3 100 µA LCLK (FWH mode) and Address Input (PP mode)=VILT/VIHT at f
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Table 13:Recommended System Power-up Timings Symbol Parameter Minimum Units TPU-READ1 Power-up to Read Operation 100 µs Power-up to Write Operation 100 µs TPU-WRITE 1 T13.2 25085 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter Table 14:Pin Impedance (VDD=3.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Tcyc Thigh 0.6 VDD Tlow 0.5 VDD 0.4 VDD p-to-p (minimum) 0.4 VDD 0.3 VDD 0.2 VDD 1161 F11.0 Figure 8: CLK Waveform AC Characteristics (FWH Mode) Table 17:Read/Write Cycle Timing Parameters, VDD =3.0-3.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Table 18:AC Input/Output Specifications, VDD =3.0-3.6V (FWH Mode) Limits Symbol Parameter IOH(AC) Switching Current High Min Max Units Test Conditions -12 VDD -17.1(VDD-VOUT) mA mA 0 < VOUT 0.3VDD 0.3VDD < VOUT < 0.9VDD 0.7VDD < VOUT
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet VDD TPRST CLK TRSTP TKRST RST#/INIT# TRSTE TRSTF TRST Sector-/Block-Erase or Program operation aborted FWH[3:0] FWH4 1161 F12.0 Figure 9: Reset Timing Diagram VTH CLK VTEST VTL TVAL FWH [3:0] (Valid Output Data) FWH [3:0] (Float Output Data) TON TOFF 1161 F13.0 Figure 10:Output Timing Parameters ©2011 Silicon Storage Technology, Inc.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet VTH VTEST CLK VTL TSU TDH FWH [3:0] (Valid Input Data) Inputs Valid VMAX 1161 F14.0 Figure 11:Input Timing Parameters Table 20:Interface Measurement Condition Parameters Symbol Value Units 1 0.6 VDD V VTL1 0.2 VDD V VTEST 0.4 VDD V VMAX1 0.4 VDD V Input Signal Edge Rate 1 V/ns VTH T20.3 25085 1. The input test environment is done with 0.1 VDD of overdrive over VIH and VIL.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet AC Characteristics (PP Mode) Table 21:Read Cycle Timing Parameters, VDD =3.0-3.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet VDD TPRST Addresses Row Address R/C# TRSTP RST# Sector-/Block-Erase or Program operation aborted TRSTE TRSTC TRSTF TRST Chip-Erase aborted DQ7-0 1161 F15.0 Figure 12:Reset Timing Diagram (PP Mode) TRSTP RST# TRST TRC Row Address Addresses TAS TAH Column Address TAS Row Address Column Address TAH R/C# VIH WE# TAA OE# TOH TOE TOLZ DQ7-0 High-Z TOHZ Data Valid High-Z 1161 F16.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet TRSTP RST# TRST Row Address Addresses TAS Column Address TAH TAS TAH R/C# TCWH TOEH OE# TOES TWP TWPH WE# TDS DQ7-0 TDH Data Valid 1161 F17.0 Figure 14:Write Cycle Timing Diagram (PP Mode) Addresses Row Column R/C# WE# OE# TOEP DQ7 D D# D# D 1161 F18.0 Figure 15:Data# Polling Timing Diagram (PP Mode) ©2011 Silicon Storage Technology, Inc.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Addresses Row Column R/C# WE# OE# TOET D DQ6 D 1161 F19.0 Figure 16:Toggle Bit Timing Diagram (PP Mode) Four-Byte Code for Byte-Program Addresses 5555 2AAA 5555 BA R/C# OE# TWP TWPH TBP WE# SB0 DQ7-0 SB1 AA 55 SB2 A0 BA = Byte-Program Address SB3 Internal Program Starts Data 1161 F20.0 Figure 17:Byte-Program Timing Diagram (PP Mode) ©2011 Silicon Storage Technology, Inc.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Six-Byte code for Sector-Erase Operation Addresses 5555 2AAA 5555 5555 2AAA SAX R/C# OE# TWP TSE TWPH WE# DQ7-0 SB0 SB1 SB2 AA 55 SB3 80 SB4 AA Internal Erasure Starts SB5 55 30 1161 F21.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Six-Byte code for Chip-Erase Operation Addresses 5555 2AAA 5555 5555 2AAA 5555 R/C# OE# TWP TSCE TWPH WE# DQ7-0 SB0 SB1 SB2 SB3 SB4 SB5 AA 55 80 AA 55 10 Internal Erasure Starts 1161 F23.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Three-Byte Sequence for Software ID Exit and Reset Addresses 2AAA 5555 5555 R/C# OE# TWP WE# TWPH SW0 AA DQ7-0 SW1 55 TIDA SW2 F0 1161 F25.0 Figure 22:Software ID Exit and Reset (PP Mode) VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1161 F26.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Start Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 1161 F28.0 Figure 25:Byte-Program Algorithm ©2011 Silicon Storage Technology, Inc.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Internal Timer Toggle Bit Data# Polling ByteProgram/Erase Initiated ByteProgram/Erase Initiated ByteProgram/Erase Initiated Wait TBP, TSCE, TBE or TSE Read byte Read DQ7 Read same byte Program/Erase Completed No Is DQ7 = true data Yes No Does DQ6 match Program/Erase Completed Yes Program/Erase Completed 1161 F29.0 Figure 26:Wait Options ©2011 Silicon Storage Technology, Inc.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Software Product ID Entry Command Sequence Software Product ID Exit Reset Command Sequence Write data: AAH Address: 5555H Write data: AAH Address: 5555H Write data: F0H Address: XXH Write data: 55H Address: 2AAAH Write data: 55H Address: 2AAAH Wait TIDA Write data: 90H Address: 5555H Write data: F0H Address: 5555H Return to normal operation Wait TIDA Wait TIDA Read Software ID Return to normal operation 1161 F30.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Chip-Erase Command Sequence Block-Erase Command Sequence Sector-Erase Command Sequence Write data: AAH Address: 5555H Write data: AAH Address: 5555H Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 55H Address: 2AAAH Write data: 55H Address: 2AAAH Write data: 80H Address: 5555H Write data: 80H Address: 5555H Write data: 80H Address: 5555H Write data: AAH Address: 5555H Write data: AAH Address:
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Product Ordering Information SST 49 LF XX XX 008A XXXX - 33 XX - 4C XX - EIE XXX Environmental Attribute E1 = non-Pb Package Modifier H = 32 leads I = 40 leads Package Type N = PLCC W = TSOP (type 1, die up, 8mm x 14mm) E = TSOP (type 1, die up, 10mm x 20mm) Operating Temperature C = Commercial = 0°C to +85°C Minimum Endurance 4 = 10,000 cycles Serial Access Clock Frequency 33 = 33 MHz Version A = Second Version Device Densit
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Packaging Diagrams TOP VIEW Optional Pin #1 Identifier .048 .042 .495 .485 .453 .447 2 1 32 SIDE VIEW .112 .106 .020 R. .029 x 30° MAX. .023 .040 R. .030 .042 .048 .595 .553 .585 .547 BOTTOM VIEW .021 .013 .400 .530 BSC .490 .032 .026 .050 BSC .015 Min. .095 .075 .050 BSC .140 .125 .032 .026 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet 1.05 0.95 Pin # 1 Identifier 0.50 BSC 8.10 7.90 0.27 0.17 0.15 0.05 12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80 0°- 5° 0.70 0.50 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 32-tsop-WH-7 1mm 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet 1.05 0.95 Pin # 1 Identifier 0.50 BSC 0.27 0.17 10.10 9.90 0.15 0.05 18.50 18.30 DETAIL 1.20 max. 0.70 0.50 20.20 19.80 0°- 5° Note: 1. Complies with JEDEC publication 95 MO-142 CD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 0.70 0.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet Table 24:Revision History Revision 06 Draft Changes • • • • • • 09 • • • • • • 10 • 07 08 • 11 • • A • • • • • • Date 2002 Data Book Changed Transient Voltage from -1.0V to VDD +1.0V to -2.0V to VDD +2.0V to match Intel FWH spec per IBM requirement. Added footnote for Transient Voltage. Updated footnote for Output Short Circuit Current.
8 Mbit Firmware Hub SST49LF008A A Microchip Technology Company Data Sheet ISBN:978-1-61341-713-3 © 2011 Silicon Storage Technology, Inc–a Microchip Technology Company. All rights reserved. SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc.
