Datasheet

©2011 Silicon Storage Technology, Inc. DS25041A 05/11
21
8 Mbit (x16) Multi-Purpose Flash Plus
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
A
Microchip Technology Company
Figure 8: CE# Controlled Program Cycle Timing Diagram
Figure 9: Data# Polling Timing Diagram
1434 F26.0
ADDRESSES
DQ
15-0
WE#
555 2AA 555 ADDR
XXAA XX55 XXA0 DATA
WORD
(ADDR/DATA)
OE#
CE#
RY/BY#
VALID
T
DH
T
CPH
T
AS
T
CH
T
CS
T
AH
T
CP
T
DS
T
BY
T
BR
T
BP
Note: WP# must be held in proper logic state (V
IL
or V
IH
) 1µs prior to and 1µs after
the command sequence.
X can be V
IL
or V
IH
, but no other value.
1434 F27.0
ADDRESS A
18-0
DQ
7
DATA
WE#
OE#
CE#
RY/BY#
DATA# DATA # DATA
T
OES
T
OEH
T
BY
T
CE
T
OE