Datasheet
©2011 Silicon Storage Technology, Inc. DS25041A 05/11
17
8 Mbit (x16) Multi-Purpose Flash Plus
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
A
Microchip Technology Company
Power Up Specifications
All functionalities and DC specifications are specified for a V
DD
ramp rate of greater than 1V per 100
ms (0V to 3V in less than 300 ms). If the VDD ramp rate is slower than 1V per 100 ms, a hardware
reset is required. The recommended V
DD
power-up to RESET# high time should be greater than 100
µs to ensure a proper reset.
Figure 5: Power-Up Diagram
Table 13:DC Operating Characteristics V
DD
= 2.7-3.6V
1
1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C
(room temperature), and V
DD
= 3V. Not 100% tested.
Symbol Parameter
Limits
Test ConditionsMin Max Units
I
DD
Power Supply Current Address input=V
ILT
/V
IHT
2
, at f=5 MHz,
V
DD
=V
DD
Max
2. See Figure 20
Read
3
3. The I
DD
current listed is typically less than 2mA/MHz, with OE# at V
IH.
Typical V
DD
is 3V.
18 mA CE#=V
IL
, OE#=WE#=V
IH
, all I/Os open
Program and Erase 30 mA CE#=WE#=V
IL
, OE#=V
IH
I
SB
Standby V
DD
Current 20 µA CE#=V
IHC
,V
DD
=V
DD
Max
RST#=V
DD
±0.3, WP#=V
DD
±0.3,
WE#=V
DD
±0.3
I
ALP
Auto Low Power 20 µA CE#=V
ILC
,V
DD
=V
DD
Max
All inputs=V
SS
or V
DD,
WE#=V
IHC
I
LI
Input Leakage Current 1 µA V
IN
=GND to V
DD
,V
DD
=V
DD
Max
I
LIW
Input Leakage Current
on WP# pin and RST#
10 µA WP#=GND to V
DD
or RST#=GND to V
DD
I
LO
Output Leakage Current 10 µA V
OUT
=GND to V
DD
,V
DD
=V
DD
Max
V
IL
Input Low Voltage 0.8 V V
DD
=V
DD
Min
V
ILC
Input Low Voltage (CMOS) 0.3 V V
DD
=V
DD
Max
V
IH
Input High Voltage 0.7V
DD
V
DD
+0.3 V V
DD
=V
DD
Max
V
IHC
Input High Voltage (CMOS) V
DD
-0.3 V
DD
+0.3 V V
DD
=V
DD
Max
V
OL
Output Low Voltage 0.2 V I
OL
=100 µA, V
DD
=V
DD
Min
V
OH
Output High Voltage V
DD
-0.2 V I
OH
=-100 µA, V
DD
=V
DD
Min
T13.8 25041
1434 F24.0
V
DD
RESET#
CE#
T
PU-READ
100µs
V
DD
min
0V
V
IH
T
RHR
5 0ns