Datasheet

A
Microchip Technology Company
©2011 Silicon Storage Technology, Inc. DS25041A 05/11
Data Sheet
www.microchip.com
8 Mbit (x16) Multi-Purpose Flash Plus
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Features
Organized as 512K x16
Single Voltage Read and Write Operations
2.7-3.6V for SST39VF801C/802C
3.0-3.6V for SST39LF801C/802C
Superior Reliability
Endurance: 100,000 Cycles (Typical)
Greater than 100 years Data Retention
Low Power Consumption (typical values at 5 MHz)
Active Current: 5 mA (typical)
Standby Current: 3 µA (typical)
Auto Low Power Mode: 3 µA (typical)
Hardware Block-Protection/WP# Input Pin
Top Block-Protection (top 8 KWord)
Bottom Block-Protection (bottom 8 KWord)
Sector-Erase Capability
Uniform 2 KWord sectors
Block-Erase Capability
Flexible block architecture; one 8-, two 4-, one 16-, and
fifteen 32-KWord blocks
Chip-Erase Capability
Erase-Suspend/Erase-Resume Capabilities
Hardware Reset Pin (RST#)
Latched Address and Data
Security-ID Feature
SST: 128 bits; User: 128 words
Fast Read Access Time:
70 ns for SST39VF801C/802C
55 ns for SST39LF801C/802C
Fast Erase and Word-Program:
Sector-Erase Time: 18 ms (typical)
Block-Erase Time: 18 ms (typical)
Chip-Erase Time: 40 ms (typical)
Word-Program Time: 7 µs (typical)
Automatic Write Timing
Internal V
PP
Generation
End-of-Write Detection
Toggle Bits
Data# Polling
Ready/Busy# Pin
CMOS I/O Compatibility
JEDEC Standard
Flash EEPROM Pinouts and command sets
Packages Available
48-lead TSOP (12mm x 20mm)
48-ball TFBGA (6mm x 8mm)
48-ball WFBGA (4mm x 6mm)
All devices are RoHS compliant
The SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C are 512K
x16 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST proprietary,
high performance CMOS SuperFlash® technology. The split-gate cell design and
thick-oxide tunneling injector attain better reliability and manufacturability com-
pared with alternate approaches. The SST39VF801C / SST39VF802C /
SST39LF801C / SST39LF802C write (Program or Erase) with a 2.7-3.6V power
supply. These devices conforms to JEDEC standard pinouts for x16 memories.

Summary of content (38 pages)