Datasheet

©2011 Silicon Storage Technology, Inc. DS25008A 08/11
8
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Not Recommended for New Designs
A
Microchip Technology Company
Data# Polling (DQ
7
)
When the SST39VF640xB are in the internal Program operation, any attempt to read DQ
7
will produce
the complement of the true data. Once the Program operation is completed, DQ
7
will produce true
data. Note that even though DQ
7
may have valid data immediately following the completion of an internal Write
operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subse-
quent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read
DQ
7
will produce a ‘0’. Once the internal Erase operation is completed, DQ
7
will produce a ‘1’. The
Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For
Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#)
pulse. See Figure 6 for Data# Polling timing diagram and Figure 20 for a flowchart.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any consecutive attempts to read DQ
6
will produce
alternating “1”s and “0”s, i.e., toggling between 1 and 0. When the internal Program or Erase operation
is completed, the DQ
6
bit will stop toggling. The device is then ready for the next operation. For Sector-
, Block-, or Chip-Erase, the toggle bit (DQ
6
) is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ
6
will be set to “1” if a Read operation is attempted on an Erase-Suspended Sector/Block. If Pro-
gram operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ
6
will toggle.
An additional Toggle Bit is available on DQ
2
, which can be used in conjunction with DQ
6
to check
whether a particular sector is being actively erased or erase-suspended. Table 2 shows detailed status
bits information. The Toggle Bit (DQ
2
) is valid after the rising edge of the last WE# (or CE#) pulse of
Write operation. See Figure 7 for Toggle Bit timing diagram and Figure 20 for a flowchart.
Note: DQ
7
and DQ
2
require a valid address when reading status information.
Table 2: Write Operation Status
Status DQ
7
DQ
6
DQ
2
Normal Operation Standard Program DQ
7
# Toggle No Toggle
Standard Erase 0 Toggle Toggle
Erase-Suspend
Mode
Read from Erase-Suspended Sector/Block 1 1 Toggle
Read from Non- Erase-Suspended Sector/Block Data Data Data
Program DQ
7
# Toggle N/A
T2.0 25008