Datasheet

©2011 Silicon Storage Technology, Inc. DS25008A 08/11
20
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Not Recommended for New Designs
A
Microchip Technology Company
Figure 5: CE# Controlled Program Cycle Timing Diagram
Figure 6: Data# Polling Timing Diagram
1288 F05.0
ADDRESS A
MS-0
DQ
15-0
T
DH
T
CPH
T
DS
T
CP
T
AH
T
AS
T
CH
T
CS
WE#
SW0 SW1 SW2
555 2AA 555 ADDR
XXAA XX55 XXA0 DATA
INTERNAL PROGRAM OPERATION STARTS
WORD
(ADDR/DATA)
OE#
CE#
T
BP
Note: A
MS
= Most significant address
A
MS
=A
21
for SST39VF640xB
WP# must be held in proper logic state (V
IL
or V
IH
) 1 µs prior to and 1 µs after the command sequence.
X can be V
IL
or V
IH,
but no other value.
1288 F06.0
ADDRESS A
MS-0
DQ
7
DATA DATA # DATA # DATA
WE#
OE#
CE#
T
OEH
T
OE
T
CE
T
OES
Note: A
MS
= Most significant address
A
MS
=A
21
for SST39VF640xB