Datasheet

©2011 Silicon Storage Technology, Inc. DS25008A 08/11
19
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Not Recommended for New Designs
A
Microchip Technology Company
Figure 3: Read Cycle Timing Diagram
Figure 4: WE# Controlled Program Cycle Timing Diagram
1288 F03.0
ADDRESS A
MS- 0
DQ
15-0
WE#
OE#
CE#
T
CE
T
RC
T
AA
T
OE
T
OLZ
V
IH
HIGH-Z
T
CLZ
T
OH
T
CHZ
HIGH-Z
DA TA VALIDDA TA VALID
T
OHZ
Note: A
MS
= Most significant address
A
MS
=A
21
for SST39VF640xB
1288 F04.0
ADDRESS A
MS- 0
DQ
15-0
T
DH
T
WPH
T
DS
T
WP
T
AH
T
AS
T
CH
T
CS
CE#
SW0 SW1 SW2
555 2A A 555 ADDR
XXAA XX55 XXA0 DATA
INTERNAL PROGR A M OPERATION STARTS
WORD
(ADDR/DATA)
OE#
WE#
T
BP
Note: A
MS
= Most significant address
A
MS
=A
21
for SST39VF640xB
WP# must be held in proper logic state (V
IL
or V
IH
) 1 µs prior to and 1 µs after the command sequence.
X can be V
IL
or V
IH,
but no other value.