Datasheet

16
Data Sheet
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
©2009 Silicon Storage Technology, Inc. S71384-01-000 1/09
FIGURE 9: Toggle Bits Timing Diagram
FIGURE 10: WE# Controlled Chip-Erase Timing Diagram
1384 F07.0
ADDRESS A
MS-0
DQ
6
and DQ
2
WE#
OE#
CE#
T
OE
T
OEH
T
CE
T
OES
TWO READ CYCLES
WITH SAME OUTPUTS
Note: A
MS
= Most significant address
A
MS
= A
20
for SST39VF320xB
1384 F08.0
ADDRESS A
MS-0
DQ
15-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
555 2AA 2AA555 555
XX55 XX10XX55XXAA XX80 XXAA
555
OE#
CE#
SIX-BYTE CODE FOR CHIP-ERASE
T
SCE
T
WP
Note: This device also supports CE# controlled Chip-Erase operation The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 15)
A
MS
= Most significant address
A
MS
= A
20
for SST39VF320xB
WP# must be held in proper logic state (V
IL
or V
IH
) 1 µs prior to and 1 µs after the command sequence.
X can be V
IL
or V
IH,
but no other value.