Datasheet

14
Data Sheet
32 Mbit Multi-Purpose Flash Plus
SST39VF3201B / SST39VF3202B
©2009 Silicon Storage Technology, Inc. S71384-01-000 1/09
FIGURE 5: Read Cycle Timing Diagram
FIGURE 6: WE# Controlled Program Cycle Timing Diagram
1384 F03.0
ADDRESS A
MS-0
DQ
15-0
WE#
OE#
CE#
T
CE
T
RC
T
AA
T
OE
T
OLZ
V
IH
HIGH-Z
T
CLZ
T
OH
T
CHZ
HIGH-Z
DATA VALIDDATA VALID
T
OHZ
Note: A
MS
= Most significant address
A
MS
= A
20
for SST39VF320xB
1384 F04.0
ADDRESS A
MS-0
DQ
15-0
T
DH
T
WPH
T
DS
T
WP
T
AH
T
AS
T
CH
T
CS
CE#
SW0 SW1 SW2
555 2AA 555 ADDR
XXAA XX55 XXA0 DATA
INTERNAL PROGRAM OPERATION STARTS
WORD
(ADDR/DATA)
OE#
WE#
T
BP
Note: A
MS
= Most significant address
A
MS
= A
20
for SST39VF320xB
WP# must be held in proper logic state (V
IL
or V
IH
) 1 µs prior to and 1 µs after the command sequence.
X can be V
IL
or V
IH,
but no other value.