Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsIntegrated Circuits (ICs)32 Bit 2 M x 16

Data Sheet

S71384-01-000 1/09

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

32 Mbit (x16) Multi-Purpose Flash Plus

SST39VF3201B / SST39VF3202B

FEATURES:

• Organized as 2M x16

• Single Voltage Read and Write Operations

– 2.7-3.6V

• Superior Reliability

– Endurance: 100,000 Cycles (Typical)

– Greater than 100 years Data Retention

• Low Power Consumption (typical values at 5 MHz)

– Active Current: 6 mA (typical)

– Standby Current: 4 µA (typical)

– Auto Low Power Mode: 4 µA (typical)

• Hardware Block-Protection/WP# Input Pin

– Top Block-Protection (top 32 KWord)

for SST39VF3202B

– Bottom Block-Protection (bottom 32 KWord)

for SST39VF3201B

• Sector-Erase Capability

– Uniform 2 KWord sectors

• Block-Erase Capability

– Uniform 32 KWord blocks

• Chip-Erase Capability

• Erase-Suspend/Erase-Resume Capabilities

• Hardware Reset Pin (RST#)

• Security-ID Feature

– SST: 128 bits; User: 128 words

• Fast Read Access Time:

– 70 ns

• Latched Address and Data

• Fast Erase and Word-Program:

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 35 ms (typical)

– Word-Program Time: 7 µs (typical)

• Automatic Write Timing

– Internal V

Generation

• End-of-Write Detection

– Toggle Bits

– Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pin Assignments

• Packages Available

– 48-lead TSOP (12mm x 20mm)

– 48-ball TFBGA (6mm x 8mm)

• All non-Pb (lead-free) devices are RoHS compliant

PRODUCT DESCRIPTION

The SST39VF320xB devices are 2M x16 CMOS Multi-

Purpose Flash Plus (MPF+) manufactured with SST’s pro-

prietary, high-performance CMOS SuperFlash technology.

The split-gate cell design and thick-oxide tunneling injector

attain better reliability and manufacturability compared with

alternate approaches. The SST39VF320xB write (Pro-

gram or Erase) with a 2.7-3.6V power supply. These

devices conform to JEDEC standard pin assignments for

x16 memories.

Featuring high performance Word-Program, the

SST39VF320xB devices provide a typical Word-Program

time of 7 µsec. These devices use Toggle Bit or Data# Poll-

ing to indicate the completion of Program operation. To pro-

tect against inadvertent write, they have on-chip hardware

and Software Data Protection schemes. Designed, manu-

factured, and tested for a wide spectrum of applications,

these devices are offered with a guaranteed typical endur-

ance of 100,000 cycles. Data retention is rated at greater

than 100 years.

The SST39VF320xB devices are suited for applications that

require convenient and economical updating of program,

configuration, or data memory. For all system applications,

they significantly improve performance and reliability, while

lowering power consumption. They inherently use less

energy during Erase and Program than alternative flash

technologies. The total energy consumed is a function of

the applied voltage, current, and time of application. Since

for any given voltage range, the SuperFlash technology

uses less current to program and has a shorter erase time,

the total energy consumed during any Erase or Program

operation is less than alternative flash technologies. These

devices also improve flexibility while lowering the cost for

program, data, and configuration storage applications.

The SuperFlash technology provides fixed Erase and Pro-

gram times, independent of the number of Erase/Program

cycles that have occurred. Therefore the system software

or hardware does not have to be modified or de-rated as is

necessary with alternative flash technologies, whose Erase

and Program times increase with accumulated Erase/Pro-

gram cycles.

To meet high-density, surface mount requirements, the

SST39VF320xB devices are offered in 48-lead TSOP and

48-ball TFBGA packages. See Figure 2 and Figure 3 for

pin assignments.

SST39VF640xB2.7V 64Mb (x16) MPF+ memories

Summary of content (29 pages)

PAGE 1
32 Mbit (x16) Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B SST39VF640xB2.7V 64Mb (x16) MPF+ memories Data Sheet FEATURES: • Organized as 2M x16 • Single Voltage Read and Write Operations – 2.7-3.
PAGE 2
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet Device Operation Any commands issued during the internal Program operation are ignored. During the command sequence, WP# should be statically held high or low. Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low.
PAGE 3
2 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet Chip-Erase Operation ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Data# Polling timing diagram and Figure 22 for a flowchart. The SST39VF320xB provide a Chip-Erase operation, which allows the user to erase the entire memory array to the “1” state.
PAGE 4
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet Data Protection Hardware Reset (RST#) The SST39VF320xB provide both hardware and software features to protect nonvolatile data from inadvertent writes. The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode.
PAGE 5
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet Product Identification Security ID The Product Identification mode identifies the devices as the SST39VF3201B and SST39VF3202B, and the manufacturer as SST. This mode may be accessed through software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket.
PAGE 6
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet X-Decoder Memory Address SuperFlash Memory Address Buffer & Latches Y-Decoder CE# OE# WE# WP# RESET# Control Logic I/O Buffers and Data Latches DQ15 - DQ0 1384 B1.
PAGE 7
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet TOP VIEW (balls facing down) 6 5 4 3 2 1 A13 A12 A14 A15 A16 NC DQ15 VSS A8 A10 A11 DQ7 DQ14 DQ13 DQ6 WE# RST# NC A19 DQ5 DQ12 VDD DQ4 NC WP# A18 A20 DQ2 DQ10 DQ11 DQ3 A9 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A3 A4 A2 A1 A0 CE# OE# VSS A B C D E F G H 1384 4-tfbga B1K P2.
PAGE 8
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet TABLE 5: Operation Modes Selection Mode CE# OE# WE# DQ Address Read VIL VIL VIH DOUT AIN Program VIL VIH VIL DIN AIN Erase VIL VIH VIL X1 Sector or block address, XXH for Chip-Erase Standby VIH X X High Z X X VIL X High Z/ DOUT X X X VIH High Z/ DOUT X VIL VIL VIH Write Inhibit Product Identification Software Mode See Table 6 T5.0 1384 1. X can be VIL or VIH, but no other value.
PAGE 9
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet TABLE 6: Software Command Sequence Command Sequence 1st Bus Write Cycle Addr1 Data2 2nd Bus Write Cycle Addr1 Data2 3rd Bus Write Cycle Addr1 4th Bus Write Cycle Data2 Addr1 Data2 Data AAH Word-Program 555H AAH 2AAH 55H 555H A0H WA3 Sector-Erase 555H AAH 2AAH 55H 555H 80H 555H 5th Bus Write Cycle 6th Bus Write Cycle Addr1 Data2 Addr1 Data2 2AAH 55H SAX4 50H 4 30H 10H Block-Erase 555H AAH 2AAH 55
PAGE 10
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet TABLE 7: CFI Query Identification String1 for SST39VF320xB Address 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH Data 0051H 0052H 0059H 0002H 0000H 0000H 0000H 0000H 0000H 0000H 0000H Data Query Unique ASCII string “QRY” Primary OEM command set Address for Primary Extended Table Alternate OEM command set (00H = none exists) Address for Alternate OEM extended Table (00H = none exits) T7.0 1384 1.
PAGE 11
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.
PAGE 12
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet TABLE 10: DC Operating Characteristics VDD = 2.7-3.
PAGE 13
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet AC CHARACTERISTICS TABLE 14: Read Cycle Timing Parameters VDD = 2.7-3.
PAGE 14
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet TRC TAA ADDRESS AMS-0 TCE CE# TOE OE# TOHZ TOLZ VIH WE# TCLZ TOH HIGH-Z DQ15-0 DATA VALID TCHZ DATA VALID HIGH-Z 1384 F03.0 Note: AMS = Most significant address AMS = A20 for SST39VF320xB FIGURE 5: Read Cycle Timing Diagram INTERNAL PROGRAM OPERATION STARTS TBP 555 ADDRESS AMS-0 2AA 555 ADDR TAH TDH TWP WE# TAS TWPH TDS OE# TCH CE# TCS DQ15-0 XXAA XX55 XXA0 DATA SW0 SW1 SW2 WORD (ADDR/DATA) 1384 F04.
PAGE 15
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet INTERNAL PROGRAM OPERATION STARTS TBP 555 ADDRESS AMS-0 2AA 555 ADDR TAH TDH TCP CE# TAS TDS TCPH OE# TCH WE# TCS DQ15-0 XXAA XX55 XXA0 DATA SW0 SW1 SW2 WORD (ADDR/DATA) 1384 F05.0 Note: AMS = Most significant address AMS = A20 for SST39VF320xB WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence. X can be VIL or VIH, but no other value.
PAGE 16
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet ADDRESS AMS-0 TCE CE# TOEH TOES TOE OE# WE# DQ6 and DQ2 TWO READ CYCLES WITH SAME OUTPUTS 1384 F07.0 Note: AMS = Most significant address AMS = A20 for SST39VF320xB FIGURE 9: Toggle Bits Timing Diagram TSCE SIX-BYTE CODE FOR CHIP-ERASE ADDRESS AMS-0 555 2AA 555 555 2AA 555 CE# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX10 SW0 SW1 SW2 SW3 SW4 SW5 1384 F08.
PAGE 17
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet TBE SIX-BYTE CODE FOR BLOCK-ERASE ADDRESS AMS-0 555 2AA 555 555 2AA BAX CE# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX30 SW0 SW1 SW2 SW3 SW4 SW5 Note: This device also supports CE# controlled Block-Erase operation The WE# and CE# signals are interchangeable as long as minimum timings are met.
PAGE 18
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet Three-Byte Sequence for Software ID Entry ADDRESS A14-0 555 2AA 555 0000 0001 CE# OE# TIDA TWP WE# TWPH DQ15-0 TAA XXAA XX55 XX90 SW0 SW1 SW2 00BF Device ID 1384 F11.0 Note: Device ID = 235DH for SST39VF3201B and 235CH for SST39VF3202B WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence. X can be VIL or VIH, but no other value.
PAGE 19
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET ADDRESS A14-0 DQ15-0 555 2AA XXAA 555 XX55 XXF0 TIDA CE# OE# TWP WE# TWHP SW0 SW1 1384 F13.0 SW2 Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence. X can be VIL or VIH, but no other value.
PAGE 20
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet TRP RST# CE#/OE# TRHR 1384 F15.0 FIGURE 17: RST# Timing Diagram (When no internal operation is in progress) TRP RST# TRY CE#/OE# End-of-Write Detection (Toggle-Bit) 1384 F16.0 FIGURE 18: RST# Timing Diagram (During Program or Erase operation) ©2009 Silicon Storage Technology, Inc.
PAGE 21
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1384 F17.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
PAGE 22
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet Start Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XXA0H Address: 555H Load Word Address/Word Data Wait for end of Program (TBP,? Data# Polling bit, or Toggle bit operation) Program Completed X can be VIL or VIH, but no other value 1384 F19.0 FIGURE 21: Word-Program Algorithm ©2009 Silicon Storage Technology, Inc.
PAGE 23
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet Internal Timer Toggle Bit Data# Polling Program/Erase Initiated Program/Erase Initiated Program/Erase Initiated Wait TBP, TSCE, TSE or TBE Read word Read DQ7 Read same word Program/Erase Completed No Is DQ7 = true data? Yes No Does DQ6 match? Program/Erase Completed Yes Program/Erase Completed 1384 F20.0 FIGURE 22: Wait Options ©2009 Silicon Storage Technology, Inc.
PAGE 24
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet CFI Query Entry Command Sequence Sec ID Query Entry Command Sequence Software Product ID Entry Command Sequence Load data: XXAAH Address: 555H Load data: XX98H Address: 55H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Wait TIDA Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX98H Address: 555H Read CFI data Load data: XX88H Address: 555H Load data:
PAGE 25
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet Software ID Exit/CFI Exit/Sec ID Exit Command Sequence Load data: XXAAH Address: 555H Load data: XXF0H Address: XXH Load data: XX55H Address: 2AAH Wait TIDA Load data: XXF0H Address: 555H Return to normal operation Wait TIDA Return to normal operation X can be VIL or VIH, but no other value 1384 F22.0 FIGURE 24: Software ID/CFI Exit Command Flowcharts ©2009 Silicon Storage Technology, Inc.
PAGE 26
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet Chip-Erase Command Sequence Sector-Erase Command Sequence Block-Erase Command Sequence Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX80H Address: 555H Load data: XX80H Address: 555H Load data: XX80H Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555
PAGE 27
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet PRODUCT ORDERING INFORMATION SST 39 XX VF 320 2B XX XXX XB - 70 XX - 4C XX - EK E XX X Environmental Attribute E1 = non-Pb Package Modifier K = 48 balls or leads Package Type E = TSOP (type1, die up, 12mm x 20mm) B3 = TFBGA (6mm x 8mm, 0.
PAGE 28
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet PACKAGING DIAGRAMS 1.05 0.95 Pin # 1 Identifier 0.50 BSC 0.27 0.17 12.20 11.80 0.15 0.05 18.50 18.30 DETAIL 1.20 max. 0.70 0.50 20.20 19.80 0°- 5° Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
PAGE 29
32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet TOP VIEW BOTTOM VIEW 8.00 ± 0.20 5.60 0.45 ± 0.05 (48X) 0.80 6 6 5 5 4.00 4 4 6.00 ± 0.20 3 3 2 2 1 1 0.80 A B C D E F G H A1 CORNER SIDE VIEW H G F E D C B A A1 CORNER 1.10 ± 0.10 0.12 SEATING PLANE 1mm 0.35 ± 0.05 Note: 1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4.