Datasheet

©2011 Silicon Storage Technology, Inc. DS25040A 05/11
17
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Data Sheet
A
Microchip Technology Company
Figure 4: Read Cycle Timing Diagram
Figure 5: WE# Controlled Program Cycle Timing Diagram
1243 F02.0
ADDRESS A
MS-0
DQ
15-0
WE#
OE#
CE#
T
CE
T
RC
T
AA
T
OE
T
OLZ
V
IH
HIGH-Z
T
CLZ
T
OH
T
CHZ
HIGH-Z
DATA VALIDDATA VALID
T
OHZ
Note: A
MS
= Most Significant Address
A
MS
=A
20
for SST39VF168x
1243 F03.2
ADDRESS A
MS-0
DQ
7-0
T
DH
T
WPH
T
DS
T
WP
T
AH
T
AS
T
CH
T
CS
CE#
SW0 SW1 SW2
AAA AAA555 ADDR
AA 55 A0 DATA
INTERNAL PROGRAM OPERATION STARTS
BYTE
(ADDR/DATA)
OE#
WE#
T
BP
Note: A
MS
= Most Significant Address
A
MS
=A
20
for SST39VF168x
WP# must be held in proper logic state (V
IL
or V
IH
) 1 µs prior to and 1 µs after the command sequence.
X can be V
IL
or V
IH,
but no other value.