Datasheet

18
Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
©2010 Silicon Storage Technology, Inc. S71380-04-000 05/10
FIGURE 10: Toggle Bits Timing Diagram
FIGURE 11: WE# Controlled Chip-Erase Timing Diagram
1380 F07.0
ADDRESS A
MS-0
DQ
6
and DQ
2
WE#
OE#
CE#
T
OE
T
OEH
T
CE
T
OES
TWO READ CYCLES
WITH SAME OUTPUTS
Note: A
MS
= Most significant address
A
MS
= A
19
1380 F31.0
ADDRESSES
DQ
15-0
WE#
555 2AA 2AA555 555
XX55
XX10
XX55XXAA
XX80
XXAA
555
OE#
CE#
RY/BY#
VALID
SIX-BYTE CODE FOR CHIP-ERASE
T
OEH
T
SCE
T
BY
T
BR
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchange-
able as long as minimum timings are met. (See Table 16).
WP# must be held in proper logic state (V
IH
) 1µs prior to and 1µs after the command sequence.
X can be V
IL
or V
IH
, but no other value.