Datasheet

16
Data Sheet
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
©2010 Silicon Storage Technology, Inc. S71380-04-000 05/10
FIGURE 6: Read Cycle Timing Diagram
FIGURE 7: WE# Controlled Program Cycle Timing Diagram
1380 F03.0
ADDRESS A
MS-0
DQ
15-0
WE#
OE#
CE#
T
CE
T
RC
T
AA
T
OE
T
OLZ
V
IH
HIGH-Z
T
CLZ
T
OH
T
CHZ
HIGH-Z
DATA VALIDDATA VALID
T
OHZ
Note: A
MS
= Most significant address
A
MS
= A
19
1380 F25.0
ADDRESSES
DQ
15-0
CE#
555 2AA 555 ADDR
XXAA XX55 XXA0 DATA
WORD
(ADDR/DATA)
OE#
WE#
RY/BY#
VALID
T
DH
T
WPH
T
AS
T
CH
T
CS
T
AH
T
WP
T
DS
T
BY
T
BR
T
BP
Note: WP# must be held in proper logic state (V
IL
or V
IH
) 1µs prior to and 1µs after the command sequence.
X can be V
IL
or V
IH
, but no other value.