Datasheet

©2011 Silicon Storage Technology, Inc. DS25028A 08/11
20
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
Not Recommended for New Designs
A
Microchip Technology Company
Figure 8: Toggle Bits Timing Diagram
Figure 9: WE# Controlled Chip-Erase Timing Diagram
1223 F07.4
ADDRESS A
MS-0
DQ
6
and DQ
2
WE#
OE#
CE#
T
OE
T
OEH
T
CE
T
OES
TWO READ CYCLES
WITH SAME OUTPUTS
Note: A
MS
= Most significant address
A
MS
=A
19
for SST39VF1601/1602 and A
20
for SST39VF3201/3202
1223 F08.5
ADDRESS A
MS-0
DQ
15-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
5555 2AAA 2AAA5555 5555
XX55 XX10XX55XXAA XX80 XXAA
5555
OE#
CE#
SIX-BYTE CODE FOR CHIP-ERASE
T
SCE
T
WP
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 17)
A
MS
= Most significant address
A
MS
=A
19
for SST39VF1601/1602 and A
20
for SST39VF3201/3202
WP# must be held in proper logic state (V
IH
) 1 µs prior to and 1 µs after the command sequence
X can be V
IL
or V
IH,
but no other value