Datasheet

©2011 Silicon Storage Technology, Inc. DS25028A 08/11
19
16 Mbit / 32 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201
SST39VF1602 / SST39VF3202
Not Recommended for New Designs
A
Microchip Technology Company
Figure 6: CE# Controlled Program Cycle Timing Diagram
Figure 7: Data# Polling Timing Diagram
1223 F05.4
ADDRESS A
MS-0
DQ
15-0
T
DH
T
CPH
T
DS
T
CP
T
AH
T
AS
T
CH
T
CS
WE#
SW0 SW1 SW2
5555 2AAA 5555 ADDR
XXAA XX55 XXA0 DATA
INTERNAL PROGRAM OPERATION STARTS
WORD
(ADDR/DATA)
OE#
CE#
T
BP
Note: A
MS
= Most significant address
A
MS
=A
19
for SST39VF1601/1602 and A
20
for SST39VF3201/3202
WP# must be held in proper logic state (V
IL
or V
IH
) 1 µs prior to and 1 µs after the command sequence
X can be V
IL
or V
IH,
but no other value
1223 F06.3
ADDRESS A
MS-0
DQ
7
DATA DATA # DATA # DATA
WE#
OE#
CE#
T
OEH
T
OE
T
CE
T
OES
Note: A
MS
= Most significant address
A
MS
=A
19
for SST39VF1601/1602 and A
20
for SST39VF3201/3202