Datasheet

©2013 Silicon Storage Technology, Inc. DS25022B 04/13
17
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
Data Sheet
Figure 11:WE# Controlled Chip-Erase Timing Diagram
Figure 12:Software ID Entry and Read
1147 F17.1
ADDRESS A
MS-0
DQ
7-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
5555 2AAA 2AAA5555 5555
55 1055AA 80 AA
5555
OE#
CE#
SIX-BYTE CODE FOR CHIP-ERASE
T
SCE
T
WP
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchangeable
as long as minimum timings are met. (See Table 10)
SA
X
X
= Sector Address
Toggled bit output is always high first.
A
MS
= Most significant address
1147 F09.2
ADDRESS A
14-0
T
IDA
DQ
7-0
WE#
SW0
SW1 SW2
5555 2AAA 5555 0000 0001
OE#
CE#
Three-byte Sequence for
Software ID Entry
T
WP
T
WPH
T
AA
BF Device ID55AA 90
Note: Device ID = B5H for SST39SF010A, B6H for SST39SF020A, and B7H for SST39SF040