Datasheet

©2011 Silicon Storage Technology, Inc. DS25001A 03/11
21
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
A
Microchip Technology Company
Figure 11: WE# Controlled Block-Erase Timing Diagram
Figure 12: WE# Controlled Sector-Erase Timing Diagram
1117 F17.9
ADDRESS A
MS-0
DQ
15-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
5555 2AAA 2AAA5555 5555
XX55 XX50XX55XXAA XX80 XXAA
BA
X
OE#
CE#
SIX-BYTE CODE FOR BLOCK-ERASE
T
BE
T
WP
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 16)
BA
X
= Block Address
A
MS
= Most significant address
A
MS
=A
16
for SST39LF/VF200A, A
17
for SST39LF/VF400A and A
18
for SST39LF/VF800A
X can be V
IL
or V
IH
, but no other value.
1117 F18.8
ADDRESS A
MS-0
DQ
15-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
5555 2AAA 2AAA5555 5555
XX55 XX30XX55XXAA XX80 XXAA
SA
X
OE#
CE#
SIX-BYTE CODE FOR SECTOR-ERASE
T
SE
T
WP
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 16)
SA
X
= Sector Address
A
MS
= Most significant address
A
MS
=A
16
for SST39LF/VF200A, A
17
for SST39LF/VF400A and A
18
for SST39LF/VF800A
X can be V
IL
or V
IH
, but no other value.