Datasheet

©2011 Silicon Storage Technology, Inc. DS-25015A 04/11
41
64 Mbit (x16) Advanced Multi-Purpose Flash Plus
SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404
Data Sheet
A
Microchip Technology Company
Figure 13:WE# Controlled Chip-Erase Timing Diagram
1309 F08.1
ADDRESS A
MS-0
DQ
15-0
WE#
SW0
SW1
SW2
SW3
SW4
SW5
555 2AA 2AA555 555
XX55 XX10XX55XXAA XX80 XXAA
555
OE#
CE#
RY/BY#
T
WP
SIX-BYTE CODE FOR CHIP-ERASE
T
SCE
T
BUSY
Note: This device also supports CE# controlled Chip-Erase operation The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 24)
A
MS
= Most significant address
A
MS
=A
21
for SST38VF6401/6402/6403/6404
WP# must be held in proper logic state (V
IL
or V
IH
) 1 µs prior to and 1 µs after the command sequence.
X can be V
IL
or V
IH,
but no other value.